Store-to-load forwarding for processor pipelines
US-12554650-B2 · Feb 17, 2026 · US
This page is not indexed by search engines while we improve data quality.
Ingalls John patents
Ingalls John is listed as an inventor on 28 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Ingalls John |
| Total patents | 28 |
| First publication | Jan 9, 2020 |
| Latest publication | Feb 17, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Error management in system on a chip with securely partitioned memory space
US-12517841-B2 · Jan 6, 2026 · US
Logging guest physical address for memory access faults
US-2025335367-A1 · Oct 30, 2025 · US
Translation lookaside buffer (TLB) prefetcher with multi-level TLB prefetches and feedback architecture
US-12399837-B2 · Aug 26, 2025 · US
Logging guest physical address for memory access faults
US-12367154-B2 · Jul 22, 2025 · US
Configuring a prefetcher associated with a processor core
US-2024338219-A1 · Oct 10, 2024 · US
Store-to-load forwarding for processor pipelines
US-2024338321-A1 · Oct 10, 2024 · US
Error Management In System On A Chip With Securely Partitioned Memory Space
US-2024303205-A1 · Sep 12, 2024 · US
Method for executing atomic memory operations when contested
US-12066941-B2 · Aug 20, 2024 · US
Bit pattern matching hardware prefetcher
US-2024184581-A1 · Jun 6, 2024 · US
Recent patents
Latest publications not already listed above.
Atomic memory operations for address translation
US-2024104024-A1 · Mar 28, 2024 · US
Translation lookaside buffer (tlb) prefetcher with multi- level tlb prefetches and feedback architecture
US-2023418763-A1 · Dec 28, 2023 · US
Data cache with prediction hints for cache hits
US-11847060-B2 · Dec 19, 2023 · US
Configuring a component of a processor core based on an attribute of an operating system process
US-2023333861-A1 · Oct 19, 2023 · US
Data cache with prediction hints for cache hits
US-2023205703-A1 · Jun 29, 2023 · US
Data cache with hybrid writeback and writethrough
US-11687455-B2 · Jun 27, 2023 · US
Logging Guest Physical Address for Memory Access Faults
US-2023195647-A1 · Jun 22, 2023 · US
Data cache with prediction hints for cache hits
US-11620229-B2 · Apr 4, 2023 · US
Method for executing atomic memory operations when contested
US-2023033550-A1 · Feb 2, 2023 · US
Data cache with hybrid writeback and writethrough
US-2023029660-A1 · Feb 2, 2023 · US
Method for executing atomic memory operations when contested
US-11467962-B2 · Oct 11, 2022 · US
Data cache with hybrid writeback and writethrough
US-11467961-B2 · Oct 11, 2022 · US
Method for executing atomic memory operations when contested
US-2022066936-A1 · Mar 3, 2022 · US
Data cache with hybrid writeback and writethrough
US-2021286724-A1 · Sep 16, 2021 · US
Data cache with prediction hints for cache hits
US-2021263854-A1 · Aug 26, 2021 · US
Data cache with hybrid writeback and writethrough
US-11023375-B1 · Jun 1, 2021 · US
Method, apparatus, and system for acceleration of inversion of injective operations
US-10866809-B2 · Dec 15, 2020 · US
Method, apparatus, and system for acceleration of inversion of injective operations
US-2020012498-A1 · Jan 9, 2020 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Sifive Inc | 26 |
| Qualcomm Inc | 2 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06F2212/1024 | 14 |
| G06F12/0862 | 6 |
| G06F12/1009 | 6 |
| G06F2212/1021 | 6 |
| G06F2212/1008 | 5 |