Multi-stage array based vertically integrated power delivery

Patent metadata

Field	Value
Publication number	US-12554302-B2
Application number	US-202218683342-A
Country	US
Kind code	B2
Filing date	Aug 15, 2022
Priority date	Aug 18, 2021
Publication date	Feb 17, 2026
Grant date	Feb 17, 2026

Abstract

Aspects of this disclosure relate to power delivery to chips in an array. An array of power conversion paths can be positioned vertically relative to the chips of the array. A power conversion path can convert a high voltage, low current signal to a low voltage, high current. The power conversion path can include a first power conversion stage and a second power conversion stage. The power conversion path can be implemented in a power supply module, for example.

First claim

What is claimed is:

1 . A computing system comprising:
an array of chips comprising a plurality of chips; and an array of power conversion paths comprising a plurality of power conversion paths positioned vertically relative to the plurality of chips, the plurality of power conversion paths comprising a first power conversion path, the first power conversion path comprising:
a first power conversion stage; and
a second power conversion stage configured to receive a power supply signal from the first power conversion stage, generate an output power supply signal having a lower voltage and a higher current than the power supply signal, and provide the output power supply signal to a first chip of the plurality of chips,
wherein the first power conversion stage is positioned vertically relative to the second power conversion stage.

2 . The computing system of claim 1 , wherein the second power conversion stage comprises:
first circuitry on a first printed circuit board; and second circuitry on a second printed circuit board, the second printed circuit board being stacked with the first printed circuit board, wherein electrical connections extend vertically between the first printed circuit board and the second printed circuit board.

3 . The computing system of claim 1 , wherein the first power conversion stage comprises first circuitry on one or more first printed circuit boards, the second power conversion stage comprises second circuitry on one or more second printed circuit boards, and the one or more first printed circuit boards are stacked with the one or more second printed circuit boards.

4 . The computing system of claim 1 , wherein the first power conversion stage comprises a first direct-current to direct-current converter, and the second power conversion stage comprises a second direct-current to direct-current converter.

5 . The computing system of claim 1 , wherein a plurality of power supply modules comprises the plurality of power conversion paths, and a first power supply module comprises the first power conversion path.

6 . The computing system of claim 5 , wherein the first power supply module comprises a thermal transfer structure positioned between the first power conversion stage and the second power conversion stage.

7 . The computing system of claim 5 , wherein the first power supply module comprises decoupling capacitors positioned vertically relative to the first and second power conversion stages.

8 . The computing system of claim 5 , wherein each of the power supply modules has an area corresponding to a footprint of a respective one of the plurality of chips.

9 . The computing system of claim 1 , wherein the first power conversion stage is configured to receive an input power supply signal having a voltage in a range from 40 Volts to 60 Volts, and the output power supply signal has a voltage of less than 1 Volt.

10 . The computing system of claim 1 , wherein the output power supply signal has a voltage of less than 1 Volt and a current on an order of a hundred Amperes.

11 . The computing system of claim 1 , wherein a system on a wafter comprises the array of chips, and the computing system comprises a wafer level packaging structure.

12 . A computing system comprising:
an array of chips comprising a plurality of chips; and an array of power conversion paths comprising a plurality of power conversion paths positioned vertically relative to the plurality of chips, the plurality of power conversion paths comprising a first power conversion path, the first power conversion path comprising:
a first power conversion stage; and
a second power conversion stage configured to receive a power supply signal from the first power conversion stage, generate an output power supply signal having a lower voltage and a higher current than the power supply signal, and provide the output power supply signal to a first chip of the plurality of chips, wherein a plurality of power supply modules comprises the plurality of power conversion paths and a first power supply module comprises the first power conversion path, and wherein the first power supply module comprises a clock circuit and filters on a printed circuit board positioned vertically relative to the first and second power conversion stages.

13 . The computing system of claim 12 , wherein the first power conversion stage is vertically integrated with the second power conversion stage.

14 . A method of power supply generation in a computing system, the method comprising:
converting, with a first power conversion stage of a power supply module of an array of power supply modules, an input power supply signal to an intermediate power supply signal, wherein the intermediate power supply signal has a lower current and a higher voltage than the input power supply signal; generating, with a second power conversion stage of the power supply module, an output power supply signal based on the intermediate power supply signal, wherein the output power supply signal has a lower current and a higher voltage than the intermediate power supply signal; and providing the output power supply signal to a chip of an array of chips by way of at least an electrical interconnect that extends vertically between the power supply module and the chip, wherein the power supply module is positioned vertically relative to the chip, and wherein the first power conversion stage and the second power conversion stage are each positioned vertically relative to the chip.

15 . The method of claim 14 , wherein the second power conversion stage comprises:
first circuitry on a first printed circuit board; and second circuitry on a second printed circuit board, the second printed circuit board being stacked with the first printed circuit board, wherein electrical connections extend vertically between the first printed circuit board and the second printed circuit board.

16 . The method of claim 14 , wherein each power supply module of the array of power supply modules has an area corresponding to a footprint of a respective chip of the array of chips.

17 . The method of claim 14 , further comprising dissipating heat using a thermal transfer structure position positioned between the first power conversion stage and the second power conversion stage.

18 . The method of claim 14 , wherein the input power supply signal has a voltage in a range from 40 Volts to 60 Volts, and the output power supply signal has a voltage of less than 1 Volt.

19 . The method of claim 14 , wherein a system on a wafter comprises the array of chips.

20 . The method of claim 14 , further comprising performing neural network training using the array of chips.

21 . The method of claim 14 , wherein the power supply module comprises a clock circuit and filters on a printed circuit board positioned vertically relative to the first and second power conversion stages.

Assignees

• Tesla Inc

Inventors

• Zhao Jin
• Sun Shishuang
• Sun Yang
• Krithivasan Vijaykumar
• Chang William
• Li Jianjun

Classifications

• G06F1/266 Primary

  Arrangements to supply power to external peripherals either directly from the computer or under computer control, e.g. supply of power through the communication port, computer controlled power-strips · CPC title

• G06F1/26 Primary

  Power supply means, e.g. regulation thereof (for memories G11C) · CPC title