Memory device using data strobe signal and method for compensating skew of data strobe signal thereof

Patent metadata

Field	Value
Publication number	US-12548611-B2
Application number	US-202418647853-A
Country	US
Kind code	B2
Filing date	Apr 26, 2024
Priority date	Sep 26, 2023
Publication date	Feb 10, 2026
Grant date	Feb 10, 2026

Abstract

A memory device includes core dies including memory cell arrays, and a buffer die electrically connected to the core dies through one or more through silicon vias. The buffer die includes a DQS generation circuit that receives an external clock signal from an external device and generates data strobe signals based on the external clock signal for communicating data with the core dies, a DQS calibration circuit that detects a latency of each of plural rank signal that are received from the core dies based on the data strobe signals, respectively, and a coefficient decision circuit that detects a threshold voltage code of the buffer die, applies a weight to the latency of each rank signal based on the threshold voltage code to generate a weighted calibration code for each rank signal, and transmits the weighted calibration codes to respective ones of the core dies.

First claim

What is claimed is:

1 . A memory device comprising:
a plurality of core dies including memory cell arrays; and a buffer die electrically connected to the plurality of core dies through at least one through silicon via (TSV), wherein the buffer die comprises: a DQS generation circuit configured to receive an external clock signal from an external device and generate a plurality of data strobe signals based on the external clock signal for communicating data with the plurality of core dies; a DQS calibration circuit configured to detect a latency of each of a plurality of rank signals, the plurality of rank signals being received from the plurality of core dies based on the plurality of data strobe signals, respectively; and a coefficient decision circuit configured to detect a threshold voltage code of the buffer die, apply a weight to the latency of each of the plurality of rank signals based on the threshold voltage code to generate a weighted calibration code for each of the plurality of rank signals, and transmit the weighted calibration codes to respective ones of the plurality of core dies.

2 . The memory device of claim 1 , wherein each of the plurality of core dies includes a DQS skew compensator which is configured to calibrate the plurality of data strobe signals based on the weighted calibration codes to generate a plurality of calibrated data strobe signals and transmit the plurality of calibrated data strobe signals to a transmitter circuit.

3 . The memory device of claim 2 , wherein the transmitter circuit comprises:
a multiplexer configured to convert data read from each of the memory cell arrays into output data based on the plurality of calibrated data strobe signals; an adaptive equalizer configured to adaptively boost a level of the output data based on an equalizing code; and an AEQ control decoder configured to decode the weighted calibration code to generate the equalizing code and output the equalizing code to the adaptive equalizer.

4 . The memory device of claim 1 , wherein the DQS calibration circuit comprises:
a sequence detection circuit configured to detect an order of the plurality of rank signals based on phases of the plurality of rank signals and output a rank selection signal based on the order; a multiplexer configured to output a selected rank signal selected from among the plurality of rank signals based on the rank selection signal; a delay line circuit configured to delay a reference strobe signal, which is set to one of the plurality of data strobe signals, based on a count value; a replica delay line circuit configured to delay the selected rank signal by a delay amount equal to a default delay amount of the delay line circuit; a phase detector configured to detect a phase difference between a first output signal of the delay line circuit and a second output signal of the replica delay line circuit and output a phase detection signal based on the phase difference; a calibration control circuit configured to output a count control signal based on the phase detection signal; and a latency detection circuit configured to output the count value or a latency of the selected rank signal based on the count control signal.

5 . The memory device of claim 4 , wherein the sequence detection circuit comprises:
a plurality of flip-flops, an input terminal of each of the plurality of flip-flops receiving a respective one of the plurality of rank signals and a clock terminal of each of the plurality of flip-flops receiving another respective one of the plurality of rank signals; and sequence logic configured to generate the rank selection signal based on output values of the plurality of flip-flops.

6 . The memory device of claim 4 , wherein the latency detection circuit comprises:
a latency counter configured to output the count value when the count control signal is at a first level and output the latency of the selected rank signal when the count control signal is at a second level; and a latency register configured to store the latency of the selected rank signal and transmit the latency of the selected rank signal to the coefficient decision circuit.

7 . The memory device of claim 1 , wherein the coefficient decision circuit comprises:
a threshold voltage detection circuit configured to generate the threshold voltage code that corresponds to a difference between an average threshold voltage of transistors included in the buffer die, and a reference threshold voltage based on one of the plurality of data strobe signals.

8 . The memory device of claim 7 , wherein the coefficient decision circuit comprises:
a plurality of weight control circuits, each configured to apply the weight to the latency of a corresponding one of the plurality of rank signals based on the threshold voltage code to generate the weighted calibration code for the corresponding one of the plurality of rank signals, the plurality of weight control circuits being configured to transmit the weighted calibration codes corresponding to the plurality of core dies to the plurality of core dies through the at least one TSV.

9 . The memory device of claim 8 , wherein each of the plurality of weight control circuits comprises:
a threshold voltage code decoder configured to decode the threshold voltage code and output a weight selection signal; and a multiple selector configured to select one of a plurality of weights based on the weight selection signal.

10 . The memory device of claim 1 , wherein the plurality of data strobe signals comprises:
a first strobe signal; a second strobe signal configured to have a phase difference of 90 degrees from the first strobe signal; a third strobe signal configured to have a phase difference of 90 degrees from the second strobe signal; and a fourth strobe signal configured to have a phase difference of 90 degrees from the third strobe signal.

11 . A skew compensation method of a memory device, the skew compensation method comprising:
transmitting a plurality of rank signals that correspond to a plurality of data strobe signals generated in a buffer die based on an external clock signal received from an external device, from a plurality of core dies to the buffer die through at least one through silicon via (TSV); detecting an order of the plurality of rank signals based on phases of the plurality of rank signals; detecting a latency of each of the plurality of rank signals; generating a weighted calibration code for each of the plurality of core dies, based on a threshold voltage of the buffer die and the latency of each of the plurality of rank signals; and compensating for a skew of the plurality of rank signals of the plurality of core dies based on the weighted calibration codes.

12 . The skew compensation method of claim 11 , further comprising:
performing adaptive equalization for each of the plurality of core dies based on the weighted calibration codes.

13 . The skew compensation method of claim 12 , further comprising:
calibrating the plurality of data strobe signals based on the weighted calibration codes to generate a plurality of calibrated data strobe signals; converting data read from each of the plurality of core dies into output data based on the plurality of calibrated data strobe signals; adaptively boosting a level of the output data based on an equalizing code; and decoding the weighted calibration codes and outputting the equalizing code.

14 . The skew compensation method of claim 11 , wherein detecting the latency of each of the plurality of rank signals comprises:
delaying a reference strobe signal, which

Assignees

• Samsung Electronics Co Ltd
• Uif Univ Industry Foundation Yonsei Univ

Inventors

• Moon Byongmo
• You Jeonghyeok
• Jung Seong-Ook
• Kim Ji Young
• Chae Hohyun

Classifications

• G11C29/50012 Primary

  of timing · CPC title

• G11C2207/2254

  Calibration · CPC title

• G11C29/50004

  of threshold voltage · CPC title

• G11C2029/5004

  Voltage · CPC title

• G11C7/1084

  Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load · CPC title