Buffer device supporting training operations for a plurality of memory devices, and memory module and memory system each including the buffer device

Patent metadata

Field	Value
Publication number	US-10824575-B2
Application number	US-201815979625-A
Country	US
Kind code	B2
Filing date	May 15, 2018
Priority date	Sep 13, 2017
Publication date	Nov 3, 2020
Grant date	Nov 3, 2020

Abstract

A memory system and a buffer device include a structure for performing training operations for a plurality of memory devices to ensure data reliability. A memory controller is configured to control a memory operation for a plurality of memory devices. A memory module includes the plurality of memory devices and a buffer device connected between the memory devices and the memory controller. Training operations for the memory devices to be performed by the buffer device including a training block with a signal delay circuit, and the memory controller performs the training operations by controlling the training block.

First claim

What is claimed is:

1. A memory system comprising:
a memory module comprising a plurality of memory devices;
a memory controller configured to control a memory operation of the plurality of memory devices; and
a buffer device connected between the plurality of memory devices and the memory controller, the buffer device comprising a training block including a first signal delay circuit to perform training operations for the plurality of memory devices;
wherein the memory controller is configured to control the training block to perform the training operations for the plurality of memory devices and comprises a second signal delay circuit to perform training operations for the buffer device.

2. The memory system of claim 1 , wherein the memory controller is configured to compare a pattern data corresponding to training data with a sampling data generated by sampling the training data from a memory device selected as an object for the training operations for the plurality of memory devices from among the plurality of memory devices, generates a delay control signal used to control a degree of delay of the first signal delay circuit based on a result of the comparison of the pattern data with the sampling data, and transmits the delay control signal to the buffer device.

3. The memory system of claim 2 , wherein the sampling data is received from the buffer device, and the training block samples the training data using a data strobe signal for the training operations for the plurality of memory devices to generate the sampling data.

4. The memory system of claim 2 , wherein, based on the delay control signal, the first signal delay circuit delays signals used to perform the training operations for the plurality of memory devices on the selected memory device.

5. The memory system of claim 1 , wherein, when performing the training operations for the buffer device and performing the memory operation for the plurality of memory devices, the memory controller generates, based on a result of performing the training operations for the buffer device, a second timing compensation information for reference by the memory controller during a timing compensation operation for signals transmitted/received by the buffer device.

6. The memory system of claim 5 , wherein, based on the second timing compensation information, the memory controller compensates for a timing of signals to be transmitted to the buffer device and signals received from the buffer device.

7. The memory system of claim 5 , wherein, the memory controller is configured to initially perform the training operations for the buffer device, and the memory controller is further configured to subsequently perform the training operations for the plurality of memory devices by controlling operation of the training block.

8. A memory system comprising:
a memory module comprising a plurality of memory devices;
a memory controller configured to control a memory operation of the plurality of memory devices; and
a buffer device connected between the plurality of memory devices and the memory controller, the buffer device comprises a training block configured to perform training operations for the plurality of memory devices;
wherein the memory controller is configured to control the training block to perform the training operations, and
wherein, when performing a memory operation for the plurality of memory devices, the memory controller generates, based on a result of performing the training operations, a first timing compensation information for reference by the buffer device during a timing compensation operation for signals transmitted/received by the memory devices, the first timing compensation information being transmitted to the buffer device.

9. The memory system of claim 8 , wherein the signals transmitted/received by the plurality of memory devices include a first data strobe signal transmitted by the buffer device to the plurality of memory devices and a second data strobe signal received by the buffer device from the plurality of memory devices.

10. The memory system of claim 8 , wherein the first timing compensation information includes timing compensation information corresponding to each of the plurality of memory devices.

11. The memory system of claim 8 , wherein the buffer device is connected to the plurality of memory devices via at least two channels, and the first timing compensation information includes timing compensation information corresponding to each of the channels.

12. The memory system of claim 8 , wherein the buffer device compensates for a timing of signals received from the memory controller and signals received from the plurality of memory devices, based on the first timing compensation information, and transmits the signals received from the memory controller to the plurality of memory devices and the signals received from the plurality of memory devices to the memory controller.

13. A memory system comprising:
a memory controller configured to control a memory operation for a plurality of memory devices; and
a memory module including the plurality of memory devices and a buffer device connected between the plurality of memory devices and the memory controller;
wherein the buffer device includes a training block configured to perform training operations for the plurality of memory devices, and
wherein the training block performs the training operations using a first training data and a first data strobe signal each received from a target memory device for the training operations from among the plurality of memory devices, and generates a first timing compensation information for reference by the buffer device during a timing compensation operation for signals relating to a memory operation transmitted/received by the plurality of memory devices.

14. The memory system of claim 13 , wherein, when performing read training operations for the target memory device, the training block comprises:
a signal delay circuit configured to delay the first data strobe signal;
a sampling circuit configured to sample the first training data using the delayed first data strobe signal and to generate a first sampling data;
a comparison circuit configured to compare a first pattern data corresponding to the first training data with the first sampling data and to generate a first comparison result; and
a delay adjusting circuit configured to generate, based on the first comparison result, a first delay control signal used to control a degree of delay of the first data strobe signal and to provide the first delay control signal to the signal delay circuit.

15. The memory system of claim 13 , wherein, when performing write training operations for the target memory device, the training block comprises:
a sampling circuit configured to sample the first training data corresponding to a second pattern data using the first data strobe signal and to generate a second sampling data;
a comparison circuit configured to compare the second sampling data with the second pattern data and to generate a second comparison result;
a delay adjusting circuit configured to generate, based on the second comparison result, a second delay control signal used to control a degree of delay of the first data strobe signal; and
a signal delay circuit configured to delay the first data strobe signal based on the second delay control signal and to transmit the delayed first data strobe signal to the target memory device of the plurality of memory devices.

16. The memory system of claim 13 , wherein the memory controller is configured to perform training operat

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Jang-Woo
• Ihm Jeong-Don
• Jeong Byung-Hoon

Classifications

• G11C7/1084 Primary

  Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load · CPC title

• G11C7/22 Primary

  Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management · CPC title

• G11C7/1057 Primary

  Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load · CPC title

• G11C7/222

  Clock generating, synchronizing or distributing circuits within memory device · CPC title

• G11C7/1093

  Input synchronization · CPC title