Memory devices and memory systems including the same

Patent metadata

Field	Value
Publication number	US-10482937-B2
Application number	US-201816033691-A
Country	US
Kind code	B2
Filing date	Jul 12, 2018
Priority date	Jan 10, 2018
Publication date	Nov 19, 2019
Grant date	Nov 19, 2019

Abstract

A memory device that includes an interface that receives a data signal and a strobe signal from an external device, the strobe signal corresponding to the data signal; a strobe buffer that receives the strobe signal from the interface; a phase detection unit that detects a phase difference between the data signal output from the interface and the strobe signal output from the strobe buffer; a phase adjust unit that adjusts a phase of the strobe signal output from the strobe buffer based on the phase difference; and a sampling unit that samples the data signal output from the interface based on the strobe signal output from the phase adjust unit.

First claim

What is claimed is:

1. A memory device comprising:
an interface configured to receive a data signal and a strobe signal from an external device, the strobe signal corresponding to the data signal;
a strobe buffer configured to receive the strobe signal from the interface;
a phase detection unit configured to detect a phase difference between the data signal output from the interface and the strobe signal output from the strobe buffer;
a phase adjust unit configured to adjust a phase of the strobe signal output from the strobe buffer based on the phase difference; and
a sampling unit configured to sample the data signal output from the interface based on the strobe signal output from the phase adjust unit.

2. The memory device of claim 1 , wherein the data signal and the strobe signal have the same phase, as provided by the external device.

3. The memory device of claim 2 , wherein the phase difference corresponds to a delay phase difference caused by the strobe buffer.

4. The memory device of claim 2 , wherein the phase detection unit is configured to determine a compensation level of the strobe signal according to the phase difference.

5. The memory device of claim 4 , wherein the phase adjust unit is configured to adjust the phase of the strobe signal by delaying the strobe signal according to the compensation level.

6. The memory device of claim 5 , wherein the phase adjust unit includes a delay locked loop circuit configured to delay the strobe signal.

7. The memory device of claim 3 , wherein the phase adjust unit is configured to adjust the phase of the strobe signal to compensate for the delay phase difference.

8. A memory system, comprising:
a memory controller configured to output
a data signal including a plurality of pieces of data, the plurality of pieces of data including at least one piece of dummy data preceding a plurality of pieces of effective data, and
a strobe signal including a plurality of timing pulses; and

a memory device including
a strobe buffer configured to receive the strobe signal,
a phase detection unit configured to detect a phase difference between the data signal and the strobe signal output from the strobe buffer based on the at least one piece of dummy data and the strobe signal,
a phase adjust unit configured to adjust a phase of the strobe signal output from the strobe buffer according to the phase difference, and
a sampling unit configured to sample the data signal according to the strobe signal output from the phase adjust unit.

9. The memory system of claim 8 , wherein a rising edge and a falling edge of a timing pulse of the plurality of timing pulses are aligned with one of
central portions of two pieces of data of the plurality of pieces of data, and
edges of one or more pieces of data of the plurality of pieces of data, as output by the memory controller.

10. The memory system of claim 9 , wherein the phase difference includes at least one of
an initial phase difference between the data signal and the strobe signal as provided by the memory controller, and
a delay phase difference caused by the strobe buffer.

11. The memory system of claim 8 , wherein the data signal includes a plurality of pieces of dummy data.

12. The memory system of claim 8 , wherein the phase detection unit is configured to detect the phase difference based on the at least one piece of dummy data and a first timing pulse among the plurality of timing pulses.

13. The memory system of claim 12 , wherein the phase adjust unit is configured to adjust the phase of the strobe signal by aligning a rising edge and a falling edge of one or more of the plurality of timing pulses with respective central portions of the plurality of pieces of effective data.

14. The memory system of claim 10 , wherein the phase adjust unit is configured to adjust the phase of the strobe signal to compensate for the at least one of the initial phase difference and the delay phase difference.

15. A memory system, comprising:
a memory controller configured to output a plurality of data signals and a strobe signal corresponding to the plurality of data signals, each of the plurality of data signals including effective data, the effective data being delayed for a determined duration with respect to the strobe signal; and
a memory device configured to
receive the strobe signal via a strobe buffer,
replicate the strobe signal to generate a plurality of strobe signals, a quantity of strobe signals in the plurality of strobe signals corresponding to a quantity of data signals in the plurality of data signals,
adjust a phase of each of the plurality of strobe signals based on the plurality of data signals and the plurality of strobe signals, and
sample the plurality of data signals according to respective strobe signals of the plurality of strobe signals.

16. The memory system of claim 15 , wherein each of the plurality of data signals includes at least one piece of dummy data preceding the effective data, the at least one piece of dummy data being in the determined duration.

17. The memory system of claim 16 , wherein the effective data includes a plurality of pieces of effective data, the at least one piece of dummy data having the same period as each of the plurality of pieces of effective data.

18. The memory system of claim 15 , wherein the memory device includes a replication network configured to replicate the strobe signal received via the strobe buffer to generate the plurality of strobe signals.

19. The memory system of claim 18 , wherein the replication network includes a plurality of buffers.

20. The memory system of claim 19 , wherein the memory device is configured to adjust the phase of each of the plurality of strobe signals to compensate for at least one of
an initial phase difference between the plurality of data signals and the strobe signal as provided by the memory controller, and
a delay phase difference generated by the strobe buffer and the plurality of buffers of the replication network.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Jang Woo
• Ihm Jeong Don
• Jeong Byung Hoon

Classifications

• G11C11/4093

  Input/output [I/O] data interface arrangements, e.g. data buffers · CPC title

• G11C11/4076

  Timing circuits (for regeneration management G11C11/406) · CPC title

• G11C7/1093

  Input synchronization · CPC title

• G11C7/227

  Timing of memory operations based on dummy memory elements or replica circuits · CPC title

• G11C7/225 Primary

  Clock input buffers · CPC title