Semiconductor memory device and memory system including the same

Patent metadata

Field	Value
Publication number	US-11699472-B2
Application number	US-202117526398-A
Country	US
Kind code	B2
Filing date	Nov 15, 2021
Priority date	Apr 21, 2021
Publication date	Jul 11, 2023
Grant date	Jul 11, 2023

Abstract

A semiconductor memory device includes a quadrature error correction circuit, a clock generation circuit and a data input/output (I/O) buffer. The quadrature error correction circuit performs a locking operation to generate a first corrected clock signal and a second corrected clock signal by adjusting a skew and a duty error of a first through fourth clock signals generated based on a data clock signal and performs a relocking operation to lock the second corrected clock signal to the first corrected clock signal in response to a relock signal. The clock generation circuit generates an output clock signal and a strobe signal based on the first corrected clock signal and the second corrected clock signal. The data I/O buffer generates a data signal by sampling data from a memory cell array based on the output clock signal and transmits the data signal and the strobe signal to a memory controller.

First claim

What is claimed is:

1. A semiconductor memory device comprising:
a data clock buffer configured to generate first through fourth clock signals based on a data clock signal received from a memory controller;
a quadrature error correction circuit configured to receive the first through fourth clock signals, configured to perform a locking operation to generate a first corrected clock signal and a second corrected clock signal which have a phase difference of 90 degrees with respect to each other by adjusting at least one of a skew and a duty error of at least some of the first through fourth clock signals in a first operation mode based on an initialization command and configured to perform a relocking operation to lock the second corrected clock signal to the first corrected clock signal in response to a relock signal in a second operation mode;
a clock generation circuit configured to generate an output clock signal and a strobe signal based on the first corrected clock signal and the second corrected clock signal; and
a data input/output (I/O) buffer configured to generate a data signal by sampling data from a memory cell array based on the output clock signal and configured to transmit the data signal and the strobe signal to the memory controller.

2. The semiconductor memory device of claim 1 , wherein the data clock buffer is configured to generate the first through fourth clock signals by converting a level of the data clock signal to a complementary metal-oxide semiconductor (CMOS) level.

3. The semiconductor memory device of claim 1 , further comprising:
a duty cycle monitor configured to monitor duty cycles of the first corrected clock signal and the second corrected clock signal and configured to provide the relock signal to the quadrature error correction circuit based on a result of the monitoring.

4. The semiconductor memory device of claim 3 , wherein the duty cycle monitor is configured to provide the relock signal to the quadrature error correction circuit periodically.

5. The semiconductor memory device of claim 1 , wherein the quadrature error correction circuit includes:
a delay circuit configured to generate first through fourth adjusted clock signals by adjusting delays of the second through fourth clock signals with respect to the first clock signal, based on first through third control code sets;
a phase interpolator configured to generate a delayed selected clock signal by delaying a second selection clock signal having a phase difference of 90 degrees with respect to a first selected clock signal, based on a fourth control code set, the first selected clock signal and the second selected clock signal being selected from among the first through fourth adjusted clock signals;
a phase detector configured to detect a phase difference between the first selected clock signal and the delayed selected clock signal to generate an up/down signal; and
a delay control circuit configured to generate the first through fourth control code sets based on the up/down signal.

6. The semiconductor memory device of claim 5 , wherein the phase detector is configured to:
apply the relock signal to the delay control circuit based on the detected phase difference in the second operation mode; and
output a lock flag with a low level, which indicates that the second corrected clock signal is locked to the first corrected clock signal.

7. The semiconductor memory device of claim 5 , wherein the delay circuit includes:
a first delay line configured to output the first adjusted clock signal by delaying the first clock signal by a fixed delay amount;
a second delay line configured to output the second adjusted clock signal by delaying the second clock signal based on the first control code set;
a third delay line configured to output the third adjusted clock signal by delaying the third clock signal based on the second control code set; and
a fourth delay line configured to output the fourth adjusted clock signal by delaying the fourth clock signal based on the third control code set.

8. The semiconductor memory device of claim 7 , wherein the delay control circuit includes:
a first delay controller configured to adjust code values of the first control code set based on the up/down signal to provide the first control code set to the second delay line;
a second delay controller configured to adjust code values of the second control code set based on the up/down signal to provide the second control code set to the third delay line;
a third delay controller configured to adjust code values of the third control code set based on the up/down signal to provide the third control code set to the fourth delay line; and
a fourth delay controller configured to adjust code values of the fourth control code set based on the up/down signal to provide the fourth control code set to the phase interpolator.

9. The semiconductor memory device of claim 8 , wherein each of the first through fourth delay controllers is configured to store code values therein in the first operation mode and is configured to adjust code values of respective ones of the first through fourth control code sets based on the code value stored therein, in the second operation mode.

10. The semiconductor memory device of claim 8 , further comprising:
a digital loop filter configured to filter the up/down signal to provide the filtered up/down signal to the fourth delay controller and one of the first delay controller, the second delay controller and the third delay controller.

11. The semiconductor memory device of claim 5 , wherein the quadrature error correction circuit further includes:
a first multiplexer configured to select a first one of the first through fourth adjusted clock signals as the first selected clock signal based on a first selection signal; and
a second multiplexer configured to select a second of the first through fourth adjusted clock signals as the second selected clock signal based on a second selection signal, the second selected clock signal having a phase lead of 90 degrees with respect to the first selected clock signal.

12. The semiconductor memory device of claim 5 , wherein the quadrature error correction circuit further includes:
a clock selector configured to select two of the first through fourth adjusted clock signals as the first corrected clock signal and the second corrected clock signal based on a selection signal, the first corrected clock signal having a phase difference of 90 degrees with respect to the second corrected clock signal.

13. The semiconductor memory device of claim 1 , further comprising:
a control logic circuit configured to control operations of the semiconductor memory device based on one or more commands received from the memory controller,
wherein the control logic circuit is configured to apply the relock signal to the quadrature error correction circuit in response to a command from the memory controller designating the relocking operation in the second operation mode.

14. The semiconductor memory device of claim 13 , wherein the memory controller is configured to designate the relocking operation in the second operation mode based on monitoring the strobe signal.

15. The semiconductor memory device of claim 14 , wherein the memory controller is configured to designate the relocking operation periodically in the second operation mode.

16. The semiconductor memory device of claim 1 , wherein the quadrature error correction circuit is configured to:
perform the locking operation based on a binary search using a successive approximate register in the first oper

Assignees

• Samsung Electronics Co Ltd

Inventors

• Yoon Hojun
• Cho Youngchul
• Choi Youngdon
• Yoo Changsik
• Choi Junghwan

Classifications

• G11C7/222 Primary

  Clock generating, synchronizing or distributing circuits within memory device · CPC title

• G11C7/1057

  Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load · CPC title

• G11C7/1084

  Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load · CPC title

• G11C11/4076 Primary

  Timing circuits (for regeneration management G11C11/406) · CPC title

• G11C29/023 Primary

  in clock generator or timing circuitry · CPC title