Hybrid fan-out architecture with emib and glass core for heterogeneous die integration applications

Patent metadata

Field	Value
Publication number	US-2020006232-A1
Application number	US-201816024707-A
Country	US
Kind code	A1
Filing date	Jun 29, 2018
Priority date	Jun 29, 2018
Publication date	Jan 2, 2020
Grant date	—

Abstract

Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, a microelectronic device package may include a redistribution layer (RDL) and an interposer over the RDL. In an embodiment, a glass core may be formed over the RDL and surround the interposer. In an embodiment, the microelectronic device package may further comprise a plurality of dies over the interposer. In an embodiment, the plurality of dies are communicatively coupled with the interposer.

First claim

What is claimed is:

1 . A microelectronic device package, comprising:
a redistribution layer (RDL); an interposer over the RDL; a glass core over the RDL and surrounding the interposer; and a plurality of dies over the interposer, wherein the plurality of dies are communicatively coupled with the interposer.

2 . The microelectronic device package of claim 1 , further comprising:
conductive vias formed through the glass core.

3 . The microelectronic device package of claim 1 , wherein a thickness of the glass core is substantially the same as the thickness of the interposer.

4 . The microelectronic device package of claim 1 , wherein the interposer is embedded in a mold layer.

5 . The microelectronic device package of claim 4 , wherein the plurality of dies are embedded in the mold layer.

6 . The microelectronic device package of claim 1 , wherein the plurality of dies are communicatively coupled to each other by conductive traces in the interposer.

7 . The microelectronic device package of claim 1 , wherein the interposer is an active die.

8 . The microelectronic device package of claim 7 , wherein the active die comprises active devices at a first process node, and wherein the plurality of dies comprise active devices at a second process node.

9 . The microelectronic device package of claim 1 , wherein the interposer is a bridge.

10 . The microelectronic device package of claim 1 , further comprising a plurality of interposers, wherein the plurality of interposers are surrounded by the glass core.

11 . The microelectronic device package of claim 10 , wherein the plurality of interposers are communicatively coupled to each other by a bridge.

12 . The microelectronic device package of claim 11 , wherein the bridge is positioned over a surface of the plurality of interposers that is opposite from the plurality of dies.

13 . The microelectronic device package of claim 12 , wherein the bridge is within the RDL.

14 . The microelectronic device package of claim 10 , wherein the bridge is an embedded multi-die interconnect bridge (EMIB).

15 . The microelectronic device package of claim 1 , wherein a CTE of the glass core matches a CTE of a dielectric layer surrounding the interposer.

16 . A method for forming a microelectronic device package, comprising:
attaching a glass core to a glass carrier, wherein the glass carrier comprises a glass substrate, a release film, and a seed layer; forming a conductive via through the glass core; disposing an interposer over the glass carrier within the glass core; disposing a dielectric material over the interposer; forming a redistribution layer (RDL) over the dielectric layer and the glass core; detaching the glass carrier; and mounting a plurality of dies over the interposer, wherein the plurality of dies are communicatively coupled to the interposer.

17 . The method of claim 16 , wherein the interposer is an active interposer, wherein the active interposer comprises active devices at a first node, and wherein the plurality of dies comprise active devices at a second node.

18 . The method of claim 16 , wherein the glass carrier has a CTE that is substantially equal to the CTE of the interposer.

19 . The method of claim 16 , wherein the glass core has a CTE that is substantially equal to the CTE of the dielectric material.

20 . The method of claim 16 , further comprising:
disposing a plurality of interposers over the glass carrier within a perimeter of the core.

21 . The method of claim 20 , further comprising:
communicatively coupling the plurality of interposers with a bridge.

22 . A computing system, comprising:
redistribution layer (RDL); a glass core over the RDL; a plurality of first dies within a perimeter of the glass core, wherein the plurality of first dies are communicatively coupled by a bridge, and wherein the bridge is embedded in the RDL; a plurality of second dies over the first dies, wherein the plurality of first dies are communicatively coupled to the first dies; and a dielectric layer over the first dies and the second dies.

23 . The computing system of claim 22 , wherein a CTE of the glass core is substantially equal to a CTE of the dielectric layer.

24 . The computing system of claim 22 , wherein the first dies comprise active devices at a first processing node, and wherein the second dies comprise active devices at a second processing node.

25 . The computing system of claim 22 , wherein a thickness of the glass core is substantially equal to the thickness of the first dies.

Assignees

• Intel Corp

Inventors

• Pietambaram Srinivas
• Manepalli Rahul
• Duan Gang

Classifications

• H10P72/7436

  used to support a device or a wafer when forming electrical connections thereto · CPC title

• H10P72/74 Primary

  using temporarily an auxiliary support · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/291

  characterised by containers, encapsulations, or other housings for the stacked chips · CPC title

• H10W90/288

  characterised by arrangements for thermal management of the stacked chips · CPC title