Package architecture of large dies using quasi-monolithic chip layers
US-12581968-B2 · Mar 17, 2026 · US
This page is not indexed by search engines while we improve data quality.
Siers Scott E patents
Siers Scott E is listed as an inventor on 5 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Siers Scott E |
| Total patents | 5 |
| First publication | Dec 15, 2022 |
| Latest publication | Mar 17, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Scalable package architecture using reticle stitching and photonics for integrated circuits
US-12543594-B2 · Feb 3, 2026 · US
Package architecture of large dies using quasi-monolithic chip layers
US-2024063132-A1 · Feb 22, 2024 · US
Scalable package architecture using reticle stitching and photonics for zetta-scale integrated circuits
US-2023352464-A1 · Nov 2, 2023 · US
Selective routing through intra-connect bridge dies
US-2022399277-A1 · Dec 15, 2022 · US
Recent patents
Latest publications not already listed above.
No data yet.
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Intel Corp | 5 |
| Intell Corp | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H10W90/724 | 5 |
| H10W80/327 | 5 |
| H10W80/312 | 5 |
| H10W90/00 | 5 |
| H10W70/611 | 5 |