Semiconductor device

Patent metadata

Field	Value
Publication number	US-12543301-B2
Application number	US-202217719723-A
Country	US
Kind code	B2
Filing date	Apr 13, 2022
Priority date	Aug 13, 2021
Publication date	Feb 3, 2026
Grant date	Feb 3, 2026

Abstract

A semiconductor device comprises an active pattern on a substrate, a pair of first source/drain patterns on the active pattern, a pair of second source/drain patterns on top surfaces of the first source/drain patterns, a gate electrode extending across the active pattern and having sidewalls that face the first and second source/drain patterns, a first channel structure extending across the gate electrode and connecting the first source/drain patterns, and a second channel structure extending across the gate electrode and connecting the second source/drain patterns. The gate electrode includes a first lower part between a bottom surface of the first channel structure and a top surface of the active pattern, and a first upper part between a top surface of the first channel structure and a bottom surface of the second channel structure. The first lower part has a thickness greater than that of the first upper part.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
an active pattern on a substrate; a pair of first source/drain patterns on the active pattern; a pair of second source/drain patterns on top surfaces of the pair of first source/drain patterns; a gate electrode that extends across the active pattern, the gate electrode having sidewalls that face the pair of first source/drain patterns and the pair of second source/drain patterns; a first channel structure that extends across the gate electrode and connects the pair of first source/drain patterns to each other; a second channel structure that extends across the gate electrode and connects the pair of second source/drain patterns to each other; and a gate dielectric layer between the gate electrode and the first channel structure, between the gate electrode and the active pattern, and between the gate electrode and the second channel structure, wherein the gate electrode includes
a first lower part that is entirely below a bottom surface of the first channel structure, the first lower part between the bottom surface of the first channel structure and a top surface of the active pattern and further between immediately-adjacent first opposing gate dielectric layer surfaces of the gate dielectric layer, and
a first upper part between a top surface of the first channel structure and a bottom surface of the second channel structure and further between immediately-adjacent second opposing gate dielectric layer surfaces of the gate dielectric layer,
wherein the first lower part has a thickness between the immediately-adjacent first opposing gate dielectric layer surfaces, the thickness of the first lower part greater than a thickness of the first upper part between the immediately-adjacent second opposing gate dielectric layer surfaces.

2 . The semiconductor device of claim 1 , wherein
the second channel structure includes a plurality of upper semiconductor patterns that are vertically stacked, and the first channel structure includes one or more lower semiconductor patterns, wherein a quantity of the one or more lower semiconductor patterns is less than a quantity of the plurality of upper semiconductor patterns.

3 . The semiconductor device of claim 1 , wherein
the first channel structure includes
a first lower semiconductor pattern on a top surface of the first lower part; and
a second lower semiconductor pattern on a top surface of the first lower semiconductor pattern, and
the gate electrode further includes a second lower part between the first lower semiconductor pattern and the second lower semiconductor pattern, the second lower part having a thickness less than the thickness of the first lower part.

4 . The semiconductor device of claim 1 , wherein the first upper part has a top surface at a level higher than a level of bottom surfaces of the pair of second source/drain patterns.

5 . The semiconductor device of claim 1 , wherein a bottom surface of the first lower part is at a level higher than a level of bottom surfaces of the pair of first source/drain patterns.

6 . The semiconductor device of claim 1 , further comprising:
a lower inner spacer on a lateral surface of the first lower part; and an upper inner spacer on a lateral surface of the first upper part, wherein the lower inner spacer has a vertical length greater than a vertical length of the upper inner spacer.

7 . The semiconductor device of claim 1 , wherein the first lower part is electrically connected to the first upper part.

8 . The semiconductor device of claim 1 , wherein
the second channel structure includes
a first upper semiconductor pattern on a top surface of the first upper part, and
a second upper semiconductor pattern on a top surface of the first upper semiconductor pattern, and
the gate electrode further includes a second upper part between the first upper semiconductor pattern and the second upper semiconductor pattern, the second upper part having a thickness less than the thickness of the first upper part.

9 . The semiconductor device of claim 1 , further comprising a separation dielectric pattern between the first channel structure and the second channel structure,
wherein the separation dielectric pattern has a bottom surface at a level lower than a level of the top surfaces of the pair of first source/drain patterns.

10 . The semiconductor device of claim 1 , further comprising a separation dielectric pattern between the first channel structure and the second channel structure,
wherein the separation dielectric pattern has a top surface at a level higher than a level of bottom surfaces of the pair of second source/drain patterns.

11 . A semiconductor device, comprising:
an active pattern that extends in a first direction on a substrate, the first direction being parallel to a top surface of the substrate or a bottom surface of the substrate; a pair of first source/drain patterns on the active pattern; a first channel structure including at least one lower semiconductor pattern that connects the pair of first source/drain patterns to each other; a first interlayer dielectric layer on the pair of first source/drain patterns; a pair of second source/drain patterns on the first interlayer dielectric layer, the pair of second source/drain patterns vertically overlapping the pair of first source/drain patterns; a second channel structure including a plurality of upper semiconductor patterns that connect the pair of second source/drain patterns to each other; a second interlayer dielectric layer on the pair of second source/drain patterns; a gate electrode that extends across the first channel structure and the second channel structure, the gate electrode extending in a second direction that intersects the first direction; a plurality of gate spacers on sidewalls of the gate electrode; a gate capping pattern that covers a top surface of the gate electrode between the plurality of gate spacers; a plurality of inner spacers between the gate electrode and the pair of first source/drain patterns; and a gate dielectric layer between the gate electrode and the first channel structure, between the gate electrode and the active pattern, and between the gate electrode and the second channel structure, wherein the gate electrode includes
a first lower part that is entirely below a bottom surface of the first channel structure, the first lower part between the bottom surface of the first channel structure and a top surface of the active pattern and further between immediately-adjacent first opposing gate dielectric layer surfaces of the gate dielectric layer, and
a first upper part between a top surface of the first channel structure and a bottom surface of the second channel structure and further between immediately-adjacent second opposing gate dielectric layer surfaces of the gate dielectric layer,
wherein the first lower part has a thickness between the immediately-adjacent first opposing gate dielectric layer surfaces, the thickness of the first lower part greater than a thickness of the first upper part between the immediately-adjacent second opposing gate dielectric layer surfaces.

12 . The semiconductor device of claim 11 , wherein the first upper part has a top surface at a level higher than a level of bottom surfaces of the pair of second source/drain patterns.

13 . The semiconductor device of claim 11 , wherein
the first channel structure includes
a first lower semiconductor pattern on a top surface of the first lower part, and
a second lower semiconductor pattern on a top surface of the first lower semiconductor pattern, and

Assignees

• Samsung Electronics Co Ltd

Inventors

• Ha Daewon
• Kim Mingyu
• Choi Doyoung

Classifications

• H10D64/021

  using multiple gate spacer layers, e.g. bilayered sidewall spacers · CPC title

• H10D64/018

  Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates · CPC title

• H10D62/235

  of IGFETs (IGFETs having buried channels H10D30/637) · CPC title

• H10D62/151

  of IGFETs  (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713) · CPC title

• H10B10/12 Primary

  comprising a MOSFET load element · CPC title