Nanosheet transistors having different gate dielectric thicknesses on the same chip

Patent metadata

Field	Value
Publication number	US-10396169-B2
Application number	US-201715846461-A
Country	US
Kind code	B2
Filing date	Dec 19, 2017
Priority date	Jan 12, 2017
Publication date	Aug 27, 2019
Grant date	Aug 27, 2019

Abstract

Embodiments are directed to a method and resulting structures for forming thin and thick gate dielectric nanosheet transistors on the same chip. A first nanosheet stack having a first sacrificial layer between a first nanosheet and a second nanosheet is formed on a substrate. A second nanosheet stack having a first sacrificial layer between a first nanosheet and a second nanosheet is formed on the substrate. The first nanosheet of the first nanosheet stack is doped and concurrently removed with the first sacrificial layer of the first nanosheet stack and the first sacrificial layer of the second nanosheet stack.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first nanosheet stack on a substrate, the first nanosheet stack comprising a first nanosheet formed over a second nanosheet;
a second nanosheet stack on the substrate, the second nanosheet stack comprising a first nanosheet formed over a second nanosheet;
a dielectric layer formed over a channel region of the first nanosheet stack;
a first gate formed over the dielectric layer in the channel region of the first nanosheet stack;
a second gate formed over a channel region of the second nanosheet stack;
a first gate contact on the first gate; and
a second gate contact on the second gate;
wherein a distance between adjacent nanosheets in the first nanosheet stack is greater than a distance between adjacent nanosheets in the second nanosheet stack;
wherein spacers are formed between the adjacent nanosheets in the first nanosheet stack and between adjacent nanosheets in the second nanosheet stack;
wherein a length of the spacers between the adjacent nanosheets in the first nanosheet stack is greater than a length of at least one of the spacers between the adjacent nanosheets in the second nanosheet stack;
wherein the first gate comprises a high-k dielectric film formed on a surface of the dielectric layer in the channel region of the first nanosheet stack; and
wherein the length of a bottom most spacer of the spacers below the adjacent nanosheets in the first nanosheet stack is greater than the length of the at least one of the spacers between the adjacent nanosheets in the second nanosheet stack.

2. The semiconductor device of claim 1 , wherein a distance between the adjacent nanosheets in the first nanosheet stack is at least double a distance between the adjacent nanosheets in the second nanosheet stack.

3. The semiconductor device of claim 1 , wherein each nanosheet of the first and second nanosheet stacks is a silicon nanosheet.

4. The semiconductor device of claim 1 , wherein each nanosheet of the first and second nanosheet stacks comprises a thickness of about 4 nm to about 10 nm.

5. The semiconductor device of claim 1 , wherein a distance between adjacent nanosheets in the first nanosheet stack is greater than about 10 nm.

6. The semiconductor device of claim 1 , wherein the dielectric layer comprises a thickness of about 3 nm to about 10 nm.

7. The semiconductor device of claim 1 further comprising first source or drain regions formed adjacent to opposite sidewalls of the first nanosheet stack.

8. The semiconductor device of claim 7 further comprising second source or drain regions formed adjacent to opposite sidewalls of the second nanosheet stack, the first and second source or drain regions separated by an interlayer dielectric.

9. The semiconductor device of claim 1 , wherein the second gate comprises a high-k dielectric film formed on a surface of the first and second nanosheets in the channel region of the second nanosheet stack.

10. A semiconductor device comprising:
a first nanosheet field effect transistor (FET) comprising two or more vertically stacked nanosheets on a substrate;
a second nanosheet FET comprising two or more vertically stacked nanosheets on the substrate, the second nanosheet FET adjacent to the first nanosheet FET;
a thick gate dielectric layer formed over a channel region of the first nanosheet FET;
a first gate formed over the thick gate dielectric layer in the channel region of the first nanosheet FET; and
a second gate formed over a channel region of the second nanosheet FET;
wherein the thick gate dielectric layer is between the first gate and each of the two or more vertically stacked nanosheets of the first nanosheet FET;
wherein spacers are formed between the adjacent nanosheets in the first nanosheet stack and between adjacent nanosheets in the second nanosheet stack;
wherein a length of the spacers between the adjacent nanosheets in the first nanosheet stack is greater than a length of at least one of the spacers between the adjacent nanosheets in the second nanosheet stack;
wherein the first gate comprises a high-k dielectric film formed on a surface of the thick gate dielectric layer in the channel region of the first nanosheet FET; and
wherein the length of a bottom most spacer of the spacers below the adjacent nanosheets in the first nanosheet stack is greater than the length of the at least one of the spacers between the adjacent nanosheets in the second nanosheet stack.

11. The semiconductor device of claim 10 , wherein a distance between nanosheets in the first nanosheet FET is at least double a distance between nanosheets in the second nanosheet FET.

12. The semiconductor device of claim 10 , wherein each nanosheet of the first and second nanosheet FETs is a silicon nanosheet.

13. The semiconductor device of claim 10 , wherein each nanosheet of the first and second nanosheet FETs comprises a thickness of about 4 nm to about 10 nm.

14. The semiconductor device of claim 10 , wherein a distance between nanosheets in the first nanosheet stack is greater than about 10 nm.

15. The semiconductor device of claim 10 , wherein the thick gate dielectric layer comprises a thickness of about 3 nm to about 10 nm.

16. The semiconductor device of claim 10 further comprising first source or drain regions formed adjacent to opposite sidewalls of the first nanosheet FET.

17. The semiconductor device of claim 16 further comprising second source or drain regions formed adjacent to opposite sidewalls of the second nanosheet FET, the first and second source or drain regions separated by an interlayer dielectric.

18. The semiconductor device of claim 10 , wherein the second gate comprises a high-k dielectric film formed on a surface of the first and second nanosheets in the channel region of the second nanosheet FET.

Assignees

• IBM

Inventors

• Cheng Kangguo
• Li Juntao
• Wang Geng
• Zhang Qintao

Classifications

• H10P50/642

  Chemical etching · CPC title

• H10P50/242

  of Group IV materials · CPC title

• H01L21/823412

  Electricity · mapped topic

• H01L21/86

  Electricity · mapped topic

• H01L27/1211

  Electricity · mapped topic