Semiconductor device, capacitor, and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-12538495-B2
Application number	US-202118023618-A
Country	US
Kind code	B2
Filing date	Aug 24, 2021
Priority date	Sep 6, 2020
Publication date	Jan 27, 2026
Grant date	Jan 27, 2026

Abstract

A semiconductor device that can be miniaturized or highly integrated is provided. A first conductor is formed over a substrate, a ferroelectric layer is formed over the first conductor, a second conductor is formed over the ferroelectric layer while substrate heating is performed, the ferroelectric layer includes hafnium oxide and zirconium oxide, and heat treatment at 500° C. or higher is not performed after the formation of the second conductor.

First claim

The invention claimed is:

1 . A method for manufacturing a capacitor, comprising:
forming a first conductor over a substrate; forming an insulating film over the first conductor; forming a conductive film over the insulating film while substrate heating is performed; and processing the conductive film and the insulating film by a lithography method to form a second conductor and an insulator, wherein the insulator comprises hafnium oxide and zirconium oxide, and wherein the insulator comprises ferroelectricity.

2 . The method for manufacturing a capacitor, according to claim 1 ,
wherein the insulating film is deposited by a thermal atomic layer deposition method, and wherein a heat treatment at 500° C. or higher is not performed after the formation of the conductive film.

3 . The method for manufacturing a capacitor, according to claim 2 ,
wherein a precursor used in the deposition of the insulating film comprises no hydrocarbon.

4 . The method for manufacturing a capacitor, according to claim 1 ,
wherein the conductive film is deposited by a thermal atomic layer deposition method.

5 . The method for manufacturing a capacitor, according to claim 4 ,
wherein a precursor used in the deposition of the conductive film comprises no hydrocarbon.

6 . The method for manufacturing a capacitor, according to claim 1 ,
wherein a temperature of the substrate heating is set to be higher than or equal to 350° C. and lower than or equal to 450° C.

7 . A semiconductor device, comprising:
a capacitor; and a transistor electrically connected to the capacitor, wherein the capacitor comprises a first conductor, a second conductor, and a ferroelectric layer, wherein the ferroelectric layer is provided between the first conductor and the second conductor, wherein each of the ferroelectric layer and the second conductor comprises an end portion outside the first conductor, wherein the ferroelectric layer comprises hafnium oxide and zirconium oxide, and wherein the transistor comprises an oxide semiconductor in a channel formation region.

8 . The semiconductor device, according to claim 7 ,
wherein a concentration of at least one of hydrogen and carbon contained in the ferroelectric layer is lower than or equal to 5×10 20 atoms/cm 3 .

9 . The semiconductor device, according to claim 7 ,
wherein a concentration of at least one of hydrogen and carbon contained in the ferroelectric layer is lower than or equal to 1×10 20 atoms/cm 3 .

10 . The semiconductor device, according to claim 7 ,
wherein the first conductor is electrically connected to one of a source and a drain of the transistor.

11 . The semiconductor device, according to claim 7 ,
wherein a thickness of the ferroelectric layer is less than or equal to 10 nm.

12 . The semiconductor device, according to claim 7 ,
wherein the capacitor is positioned above the transistor.

13 . The semiconductor device, according to claim 12 ,
wherein a first insulator is positioned below the capacitor, wherein a second insulator is positioned to cover the capacitor, wherein the first insulator is in contact with a bottom surface of the second insulator in a region not overlapping with the capacitor, and wherein the first insulator and the second insulator each comprise silicon nitride.

14 . The semiconductor device, according to claim 12 ,
wherein a first insulator is positioned below the transistor, wherein a second insulator is positioned to cover the capacitor, wherein the first insulator is in contact with a bottom surface of the second insulator in a region not overlapping with the transistor or the capacitor, and wherein the first insulator and the second insulator each comprise silicon nitride.

15 . The semiconductor device, according to claim 13 ,
wherein the second insulator comprises a first layer and a second layer over the first layer.

16 . The semiconductor device, according to claim 7 ,
wherein an interlayer insulating film is positioned above the transistor, wherein the interlayer insulating film comprises an opening reaching any one of a source and a drain of the transistor, wherein the first conductor is positioned in contact with a side surface and a bottom surface of the opening, wherein the ferroelectric layer is positioned to cover the first conductor, and wherein the second conductor is positioned over the ferroelectric layer.

17 . A semiconductor device, comprising:
a capacitor; a transistor electrically connected to the capacitor; a first conductor functioning as one of a source and a drain of the transistor; a second conductor functioning as the other of the source and the drain of the transistor; a third conductor functioning as a first gate of the transistor; a fourth conductor functioning as a second gate of the transistor; an oxide semiconductor layer provided between the third conductor and the fourth conductor; a fifth conductor functioning as a first electrode of the capacitor; a sixth conductor functioning as a second electrode of the capacitor; and a ferroelectric layer provided between the fifth conductor and the sixth conductor, wherein, in a top view, the fourth conductor is provided inside the third conductor, wherein, in the top view, the sixth conductor overlaps with the second conductor and the oxide semiconductor layer, wherein, in the top view, the sixth conductor extends beyond a first side, a second side, and a third side of the second conductor, and wherein the ferroelectric layer comprises hafnium oxide and zirconium oxide.

18 . The semiconductor device, according to claim 17 ,
wherein the fifth conductor is embedded in the second conductor, and wherein the ferroelectric layer is in contact with a top surface and a side surface of the fifth conductor and a bottom and a side surface of the sixth conductor.

19 . The semiconductor device, according to claim 17 ,
wherein the fifth conductor is embedded in the second conductor, wherein the ferroelectric layer is in contact with a top surface and a side surface of the fifth conductor and a bottom and a side surface of the sixth conductor, and wherein the fourth conductor is provided adjacent to the fifth conductor and the sixth conductor.

Assignees

• Semiconductor Energy Lab

Inventors

• Yamazaki Shunpei
• Jinbo Yasuhiro
• Kunitake Hitoshi
• Baba Haruyuki
• Ito Yuki
• Isaka Fumito
• Tanemura Kazuki
• Yamane Yasumasa
• Onuki tatsuya

Classifications

• H10B53/30 Primary

  characterised by the memory core region · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/6755

  Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate · CPC title

• H10D30/6733

  Multi-gate TFTs · CPC title

• H10D1/682

  having dielectrics comprising perovskite structures · CPC title