Atomic layer deposition of p-type oxide semiconductor thin films

Patent metadata

Field	Value
Publication number	US-2016190290-A1
Application number	US-201414586282-A
Country	US
Kind code	A1
Filing date	Dec 30, 2014
Priority date	Dec 30, 2014
Publication date	Jun 30, 2016
Grant date	—

Abstract

Provided herein are methods of depositing p-type metal oxide thin films by atomic layer deposition (ALD). Also provided are p-type metal oxide thin films and TFTs including p-type metal oxide channels. In some implementations, the p-type metal oxide thin films have a metal and oxygen vacancy defect density of less than 10 19 /cm 3 . The p-type metal oxide thin films may be electrically active throughout the entire thicknesses of the thin films.

First claim

What is claimed is:

1 . An method of forming a thin film transistor (TFT) comprising:
providing a substrate; exposing the substrate to a pulse of a metal reactant to form an adsorbed layer of the metal reactant over the substrate; and exposing the substrate to a pulse of an oxidant to react with the adsorbed layer of the metal reactant to form a metal oxide layer, where the metal oxide layer is a tin-based (Sn-based) p-type semiconductor layer.

2 . The method of claim 1 , wherein the metal reactant is an Sn(II)-based organometallic reactant.

3 . The method of claim 1 , wherein the substrate temperature is between about 50° C. and 300° C.

4 . The method of claim 1 , wherein the oxidant is selected from the group consisting of oxygen (O 2 ), ozone (O 3 ), water (H 2 O), hydrogen peroxide (H 2 O 2 ), carbon dioxide (CO 2 ), carbon monoxide (CO), methanol (CH 3 OH), ethanol (C 2 H 6 OH), isopropyl alcohol (C 3 H 7 OH), and combinations thereof.

5 . The method of claim 1 , wherein the oxidant is a hydrogen-containing oxidant.

6 . The method of claim 5 , wherein hydrogen from the hydrogen-containing oxidant is incorporated in the metal oxide layer.

7 . The method of claim 1 , wherein the oxidant is a weak oxidant.

8 . The method of claim 1 , wherein exposing the substrate to a pulse of an oxidant includes applying plasma energy.

9 . The method of claim 1 , further comprising exposing the substrate to a second metal reactant.

10 . The method of claim 9 , wherein the Sn-based p-type semiconductor layer is a ternary Sn-based metal oxide layer.

11 . The method of claim 9 , wherein the second metal reactant is selected from the group consisting of tungsten-containing reactants, titanium-containing reactants, niobium-containing reactants, and boron-containing reactants.

12 . The method of claim 1 , further comprising exposing the substrate to a dopant pulse.

13 . The method of claim 12 , wherein the dopant is hydrogen.

14 . The method of claim 1 , further comprising forming a gate electrode and a gate dielectric, wherein the gate dielectric is between the p-type metal oxide semiconductor layer and the gate electrode.

15 . The method of claim 14 , wherein the gate electrode is formed over the metal oxide layer.

16 . The method of claim 14 , wherein the metal oxide layer is formed over the gate electrode.

17 . An apparatus comprising:
a thin film transistor (TFT) including a source electrode; a drain electrode; and a semiconductor channel connecting the source electrode and the drain electrode, the semiconductor channel including a Sn-based p-type metal oxide semiconductor, wherein the Sn-based p-type metal oxide semiconductor has a vacancy defect density of less than about 10 19 /cm 3 .

18 . The apparatus of claim 17 , wherein the thickness of the semiconductor channel is less than about 15 nm.

19 . The apparatus of claim 17 , wherein the semiconductor channel is electrically active throughout its thickness.

20 . The apparatus of claim 17 , wherein the TFT is part of a complementary metal-oxide-semiconductor (CMOS) TFT device.

21 . The apparatus of claim 17 , wherein the TFT is a bottom gate TFT.

22 . The apparatus of claim 17 , wherein the TFT is a top gate TFT.

23 . The apparatus of claim 17 , wherein the Sn-based p-type metal oxide semiconductor is an ALD-deposited layer.

24 . The apparatus of claim 17 , further comprising: a display; a processor that is configured to communicate with the display, the processor being configured to process image data; and a memory device that is configured to communicate with the processor.

25 . The apparatus of claim 17 , further comprising: a driver circuit configured to send at least one signal to the display; and a controller configured to send at least a portion of the image data to the driver circuit.

26 . The apparatus of claim 24 , wherein the driver circuit includes the TFT.

27 . The apparatus of claim 24 , further comprising: an image source module configured to send the image data to the processor, wherein the image source module includes at least one of a receiver, transceiver, and transmitter.

28 . The apparatus of claim 24 , further comprising: an input device configured to receive input data and to communicate the input data to the processor.

Assignees

• Qualcomm Mems Technologies Inc

Inventors

• Nomura Kenji
• Hong John Hyunchul

Classifications

• H10P14/3434

  being oxide semiconductor materials (Group IIB-VIA semiconductor materials H10P14/3424) · CPC title

• H10P14/3412

  including tin · CPC title

• H10P14/2922 Primary

  being non-crystalline insulating materials, e.g. glass or polymers · CPC title

• H10P14/24

  using chemical vapour deposition [CVD] · CPC title

• H10D86/423

  comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO · CPC title