Memory device with multi channel structures and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-12538488-B2
Application number	US-202318106306-A
Country	US
Kind code	B2
Filing date	Feb 6, 2023
Priority date	Aug 3, 2022
Publication date	Jan 27, 2026
Grant date	Jan 27, 2026

Abstract

A memory device, and a method of manufacturing the same, includes a stacked structure including gate lines stacked to be spaced apart from each other. The memory device also includes a first channel structure vertical to the gate lines and including a major axis in a first direction. The memory device further includes a second channel structure configured to separate the first channel structure and including a major axis in a second direction orthogonal to the first direction. The first channel structure includes a first memory cell group and a second memory cell group separated from each other by the second channel structure. The second channel structure includes a third memory cell group and a fourth memory cell group separated from each other in the second direction.

First claim

What is claimed is:

1 . A memory device, comprising:
a stacked structure including gate lines stacked to be spaced apart from each other; a first channel structure vertical to the gate lines and including a major axis in a first direction; and a second channel structure configured to separate the first channel structure, and including a major axis in a second direction orthogonal to the first direction, wherein the first channel structure comprises a first memory cell group and a second memory cell group separated from each other by the second channel structure, and wherein the second channel structure comprises a third memory cell group and a fourth memory cell group separated from each other in the second direction.

2 . The memory device according to claim 1 , wherein the second channel structure is disposed between the first memory cell group and the second memory cell group.

3 . The memory device according to claim 1 , wherein each of the first, second, third, and fourth memory cell groups includes a core pillar, a channel layer, a tunnel insulating layer, a charge trap layer, and a blocking layer that are formed in a direction vertical to the gate lines.

4 . The memory device according to claim 3 , wherein the core pillar of the third memory cell group is connected with the channel layer of the third memory cell group and the tunnel insulating layers of the third memory cell group.

5 . The memory device according to claim 3 , wherein the third and fourth memory cell groups include capping layers separated from each other by a separation pattern.

6 . The memory device according to claim 5 , wherein the separation pattern is connected to a part of the tunnel insulating layers of the third memory cell group and a part of the tunnel insulating layer of the fourth memory cell group.

7 . The memory device according to claim 5 , wherein the separation pattern comprises an insulating material.

8 . The memory device according to claim 5 , wherein a diameter of the separation pattern is equal to or greater than a length of a minor axis of a channel layer of each of the third memory cell group and the fourth memory cell group.

9 . The memory device according to claim 5 , wherein a length of a minor axis of each of the capping layers is equal to or greater than a length of a minor axis of a channel layer of each of the third memory cell group and the fourth memory cell group.

10 . The memory device according to claim 5 , wherein a length of a major axis of each of the capping layers is equal to or smaller than a length of a major axis of a channel layer of each of the third memory cell group and the fourth memory cell group.

11 . The memory device according to claim 3 , further comprising:
a compensation layer formed between the channel layer of each of the first memory cell group and the second memory cell group and the second channel structure.

12 . A method of manufacturing a memory device, the method comprising:
forming a stacked structure including gate lines on a lower structure; forming a first channel structure arranged in a direction vertical to the gate lines; forming a second channel structure configured to separate memory cells included in the first channel structure into first and second memory cell groups; and separating memory cells included in the second channel structure into third and fourth memory cell groups.

13 . The method according to claim 12 , wherein forming the first channel structure comprises:
stacking first and second material layers on the lower structure; forming a first vertical hole arranged in a direction vertical to the first and second material layers; and forming a first blocking layer, a first charge trap layer, a first tunnel insulating layer, a first channel layer, and a first core pillar along an inner wall of the first vertical hole.

14 . The method according to claim 12 , wherein:
the first channel structure is formed having a major axis in a first direction, and the second channel structure is formed having a major axis in a second direction orthogonal to the first direction.

15 . The method according to claim 12 , wherein forming the second channel structure comprises:
forming a second vertical hole configured to separate the first channel structure; and forming a second blocking layer, a second charge trap layer, a second tunnel insulating layer, and a second channel layer along an inner wall of the second vertical hole.

16 . The method according to claim 15 , wherein separating the memory cells included in the second channel structure into the third and fourth memory cell groups comprises:
forming a fourth vertical hole configured to separate the second channel layer; and forming a second core pillar along an inner wall of the fourth vertical hole.

17 . The method according to claim 15 , further comprising:
after forming the second vertical hole, forming a compensation layer connected with the first channel layer through the second vertical hole.

18 . The method according to claim 15 , further comprising:
forming a second capping layer on the second channel structure connected to the second channel layer and the second tunnel insulating layer.

19 . The method according to claim 18 , wherein separating the second capping layer comprises:
forming a fifth vertical hole configured to separate the second capping layer; and forming a separation pattern along an inner wall of the fifth vertical hole.

20 . The method according to claim 19 , wherein a length of a minor axis of the separation pattern is equal to or greater than a length of a minor axis of the second channel layer.

21 . The method according to claim 18 , wherein a length of a minor axis of the second capping layer is equal to or greater than a length of a minor axis of the second channel layer.

Assignees

• Sk Hynix Inc

Inventors

• Choi Won Geun
• Park Mi Seong
• Park In Su
• Jang Jung Shik
• Choi Jung Dal

Classifications

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B43/10

  characterised by the top-view layout · CPC title

• H10B43/50

  characterised by the boundary region between the core and peripheral circuit regions · CPC title

• H10D64/037

  comprising charge-trapping insulators · CPC title

• H10B43/35 Primary

  with cell select transistors, e.g. NAND · CPC title