Methods for forming three-dimensional memory devices with channel structures having plum blossom shape

Patent metadata

Field	Value
Publication number	US-2022013537-A1
Application number	US-202017085366-A
Country	US
Kind code	A1
Filing date	Oct 30, 2020
Priority date	Jul 8, 2020
Publication date	Jan 13, 2022
Grant date	—

Abstract

Embodiments of three-dimensional (3D) memory devices and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A channel hole extending vertically above a substrate and having a plum blossom shape in a plan view is formed. A continuous blocking layer, a continuous charge trapping layer, and a continuous tunneling layer each following the plum blossom shape are formed from outside to inside in this order along sidewalls of the channel hole. A plurality of separate semiconductor channels each disposed over part of the continuous tunneling layer at a respective apex of the plum blossom shape are formed.

First claim

What is claimed is:

1 . A method for forming a three-dimensional (3D) memory device, comprising:
forming a channel hole extending vertically above a substrate and having a plum blossom shape in a plan view; sequentially forming a blocking layer, a charge trapping layer, a tunneling layer, and a semiconductor channel layer each following the plum blossom shape along sidewalls of the channel hole; forming an etch stop layer over the semiconductor channel layer, such that an apex thickness of the etch stop layer at each apex of the plum blossom shape is greater than an edge thickness of the etch stop layer at edges of the plum blossom shape; removing parts of the etch stop layer at the edges of the plum blossom shape to expose parts of the semiconductor channel layer at the edges of the plum blossom shape; and removing the parts of the semiconductor channel layer at the edges of the plum blossom shape to separate the semiconductor channel layer into a plurality of semiconductor channels each at a respective apex of the plum blossom shape.

2 . The method of claim 1 , wherein the plum blossom shape comprises a plurality of petals, and the semiconductor channels are formed in the plurality of petals, respectively.

3 . The method of claim 2 , wherein a number of the petals or the semiconductor channels is greater than 2.

4 . The method of claim 1 , wherein sequentially forming the blocking layer, charge trapping layer, tunneling layer, and semiconductor channel layer comprises sequentially depositing layers of silicon oxide, silicon nitride, silicon oxide, and polysilicon along the sidewalls of the channel hole.

5 . The method of claim 4 , wherein the deposition comprises atomic layer deposition (ALD).

6 . The method of claim 1 , wherein a thickness of the semiconductor channel layer is nominally uniform in the plan view.

7 . The method of claim 6 , wherein the thickness of the semiconductor channel layer is between about 10 nm and about 15 nm.

8 . The method of claim 1 , wherein forming the etch stop layer comprises depositing a layer of silicon oxide over the semiconductor channel layer using ALD without filling the channel hole.

9 . The method of claim 1 , wherein removing the parts of the etch stop layer comprises wet etching the etch stop layer until the parts of the etch stop layer at the edges of the plum blossom shape are etched away, leaving a remainder of the etch stop layer at each apex of the plum blossom shape.

10 . The method of claim 9 , wherein removing the parts of the semiconductor channel layer comprises wet etching the semiconductor channel layer until being stopped by the remainder of the etch stop layer.

11 . The method of claim 1 , further comprising after removing the parts of the semiconductor channel layer, forming a capping layer to fill the channel hole.

12 . A method for forming a three-dimensional (3D) memory device, comprising:
forming a channel hole extending vertically above a substrate and having a plum blossom shape in a plan view; sequentially forming a blocking layer, a charge trapping layer, and a tunneling layer each following the plum blossom shape along sidewalls of the channel hole; forming a semiconductor channel layer over the tunneling layer, such that an apex thickness of the semiconductor channel layer at each apex of the plum blossom shape is greater than an edge thickness of the semiconductor channel layer at edges of the plum blossom shape; and removing parts of the semiconductor channel layer at the edges of the plum blossom shape to separate the semiconductor channel layer into a plurality of semiconductor channels each at a respective apex of the plum blossom shape.

13 . The method of claim 12 , wherein the plum blossom shape comprises a plurality of petals, and the semiconductor channels are formed in the plurality of petals, respectively.

14 . The method of claim 13 , wherein a number of the petals or the semiconductor channels is greater than 2.

15 . The method of claim 12 , wherein sequentially forming the blocking layer, charge trapping layer, and tunneling layer comprises sequentially depositing layers of silicon oxide, silicon nitride, and silicon oxide along the sidewalls of the channel hole.

16 . The method of claim 15 , wherein the deposition comprises atomic layer deposition (ALD).

17 . The method of claim 12 , wherein forming the semiconductor channel layer comprises depositing a layer of polysilicon over the tunneling layer using ALD without filling the channel hole.

18 . The method of claim 12 , wherein removing the parts of the semiconductor channel layer comprises wet etching or dry etching the semiconductor channel layer until the parts of the semiconductor channel layer at the edges of the plum blossom shape are etched away, leaving a remainder of the semiconductor channel layer at each apex of the plum blossom shape.

19 . The method of claim 12 , further comprising after removing the parts of the semiconductor channel layer, forming a capping layer to fill the channel hole.

20 . A method for forming a three-dimensional (3D) memory device, comprising:
forming a channel hole extending vertically above a substrate and having a plum blossom shape in a plan view; forming a continuous blocking layer, a continuous charge trapping layer, and a continuous tunneling layer each following the plum blossom shape from outside to inside in this order along sidewalls of the channel hole; and forming a plurality of separate semiconductor channels each disposed over part of the continuous tunneling layer at a respective apex of the plum blossom shape.

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Geng Wanbo
• Xue Lei
• Liu Xiaoxin
• Gao Tingting
• Cheng Weihua

Classifications

• H10D64/037 Primary

  comprising charge-trapping insulators · CPC title

• H01L27/11565

  Electricity · mapped topic

• H01L27/11582 Primary

  Electricity · mapped topic

• H10B41/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B43/10

  characterised by the top-view layout · CPC title