Three-dimensional NAND memory device with split gates

Patent metadata

Field	Value
Publication number	US-11716847-B2
Application number	US-202017113624-A
Country	US
Kind code	B2
Filing date	Dec 7, 2020
Priority date	Oct 19, 2020
Publication date	Aug 1, 2023
Grant date	Aug 1, 2023

Abstract

A semiconductor device is provided. The semiconductor device includes word line layers and insulating layers that are alternatingly stacked along a vertical direction perpendicular to a substrate of the semiconductor device. The semiconductor device includes a channel structure that extends along the vertical direction through the word line layers and the insulating layers. A cross-section of the channel structure that is perpendicular to the vertical axis includes channel layer sections that are spaced apart from one another.

First claim

What is claimed is:

1. A semiconductor device, comprising:
word line layers and insulating layers that are alternatingly stacked along a vertical direction perpendicular to a substrate of the semiconductor device; and
a channel structure that extends through the word line layers and the insulating layers along the vertical direction, the channel structure including:
a barrier layer extending in the vertical direction through ones of the word line layers and insulating layers,
a charge trapping layer formed over an inner surface of the barrier layer,
a tunneling layer formed over an inner surface of the charge trapping layer, and
a channel layer arranged over an inner surface of the tunneling layer and partitioned into channel layer sections each extending in the vertical direction through the ones of the word line layers and insulating layers, wherein

a cross-section of the channel structure that is perpendicular to the vertical direction includes the channel layer sections spaced apart from each other,
the barrier layer is continuous at an outer surface of the channel structure in the cross-section of the channel structure,
the channel layer sections are spaced apart from one another by a dielectric laver, and
the tunneling layer continuously surrounds the channel layer sections and the dielectric layer in the cross-section of the channel structure.

2. The semiconductor device of claim 1 , wherein the cross-section of the channel structure has one of an oval profile, a star profile, a trefoil profile, or a quatrefoil profile.

3. The semiconductor device of claim 2 , wherein a ratio of a first long axis of the cross-section of the channel structure and a first short axis of the cross-section of the channel structure is in a range of ½ to ⅗.

4. The semiconductor device of claim 3 , wherein a first pair of the channel layer sections are separately arranged along the first long axis of the cross-section of the channel structure.

5. The semiconductor device of claim 3 , wherein a second pair of the channel layer sections are separately arranged along a second long axis of the cross-section.

6. A semiconductor device, comprising:
an array region and a staircase region that are positioned adjacent each other and foamed in a stack of alternating word line layers and insulating layers that is formed over a substrate of the semiconductor device;
a channel structure that is disposed in the array region and extends through the stack along a vertical direction perpendicular to the substrate, the channel structure including:
a barrier layer extending in the vertical direction through ones of the word line layers and insulating layers,
a charge trapping layer formed over an inner surface of the barrier layer,
a tunneling layer formed over an inner surface of the charge trapping layer, and
a channel layer arranged over an inner surface of the tunneling layer and partitioned into channel layer sections each extending in the vertical direction through the ones of the word line layers and insulating layers; and

word line contacts formed in the staircase region, the word line contacts extending from the word line layers of the staircase region along the vertical direction, wherein
a cross-section of the channel structure that is perpendicular to the vertical direction includes the channel layer sections spaced apart from one another,
the barrier layer is continuous at an outer surface of the channel structure in the cross-section of the channel structure,
the channel layer sections spaced apart from one another by a dielectric layer, and
the tunneling layer continuously surrounds the channel layer sections and the dielectric layer in the cross-section of the channel structure.

7. The semiconductor device of claim 6 , wherein the cross-section of the channel structure has one of an oval profile, a star profile, a trefoil profile, or a quatrefoil profile.

8. The semiconductor device of claim 7 , wherein a ratio of a first long axis of the cross-section of the channel structure and a first short axis of the cross-section of the channel structure is in a range of ½ to ⅗.

9. The semiconductor device of claim 8 , wherein a first pair of the channel layer sections are separately arranged along the first long axis of the cross-section of the channel structure.

10. The semiconductor device of claim 8 , wherein a second pair of the channel layer sections are separately arranged along a second long axis of the cross-section.

11. A semiconductor device, comprising:
word line layers and insulating layers that are alternatingly stacked along a vertical direction perpendicular to a substrate of the semiconductor device; and
a channel structure that extends through the word line layers and the insulating layers along the vertical direction, the channel structure including:
a barrier layer extending in the vertical direction through ones of the word line layers and insulating layers,
a charge trapping layer formed over an inner surface of the barrier layer,
a tunneling layer formed over an inner surface of the charge trapping layer, and
a channel layer arranged over an inner surface of the tunneling layer and partitioned into channel layer sections each extending in the vertical direction through the ones of the word line layers and insulating layers, wherein

a cross-section of the channel structure that is perpendicular to the vertical direction includes the channel layer sections spaced apart from each other,
the barrier layer is continuous at an outer surface of the channel structure in the cross-section of the channel structure,
the tunneling layer is partitioned into tunneling layer sections each extending in the vertical direction through the ones of the word line layers and insulating layers,
the tunneling layer sections are spaced apart from one another by a dielectric layer in the cross section of the channel structure, and
the charge trapping layer continuously surrounds the tunneling layer sections and the dielectric layer in the cross section of the channel structure.

12. The semiconductor device of claim 11 , wherein the cross-section of the channel structure has one of an oval profile, a star profile, a trefoil profile, or a quatrefoil profile.

13. The semiconductor device of claim 12 , wherein a ratio of a first long axis of the cross-section of the channel structure and a first short axis of the cross-section of the channel structure is in a range of ½ to ⅗.

14. The semiconductor device of claim 13 , wherein a first pair of the channel layer sections are separately arranged along the first long axis of the cross-section of the channel structure.

15. The semiconductor device of claim 13 , wherein a second pair of the channel layer sections are separately arranged along a second long axis of the cross-section.

16. A semiconductor device, comprising:
an array region and a staircase region that are positioned adjacent each other and formed in a stack of alternating word line layers and insulating layers that is formed over a substrate of the semiconductor device;
a channel structure that is disposed in the array region and extends through the stack along a vertical direction perpendicular to the substrate, the channel structure including:
a barrier layer extending in the vertical direction through ones of the word line layers and insulating layers,
a charge trapping layer formed over an inner surface of the barrier layer,
a tunneling layer formed over an inner surface of the charge trapping layer, and
a channel layer arranged over an inner surface of the tunneling layer and

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Gao Tingting
• Xue Lei
• Liu Xiaoxin
• Geng Wanbo

Classifications

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10D64/037

  comprising charge-trapping insulators · CPC title

• H10D30/694

  characterised by the shapes, relative sizes or dispositions of the gate electrodes · CPC title

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H01L23/5226

  Electricity · mapped topic