Semiconductor device and memory system including multiple conductive layers

Patent metadata

Field	Value
Publication number	US-12538481-B2
Application number	US-202117566832-A
Country	US
Kind code	B2
Filing date	Dec 31, 2021
Priority date	Jul 14, 2021
Publication date	Jan 27, 2026
Grant date	Jan 27, 2026

Abstract

Provided is a semiconductor device. The semiconductor device includes: a plurality of insulating layers and a plurality of gate electrodes alternately arranged in a first direction; and a plurality of channel structures passing through the plurality of gate electrodes and the plurality of insulating layers in the first direction, wherein each of the plurality of gate electrodes includes: a first conductive layer including an inner wall surrounding the plurality of channel structures; and a second conductive layer that is separated from the plurality of channel structures in a second direction perpendicular to the first direction, wherein resistivity of the second conductive layer is less than resistivity of the first conductive layer.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a plurality of insulating layers and a plurality of gate electrodes alternately arranged in a first direction; and a plurality of channel structures passing through the plurality of gate electrodes and the plurality of insulating layers in the first direction, wherein each of the plurality of gate electrodes comprises: a first metal layer comprising an inner wall surrounding the plurality of channel structures; and a second metal layer that is separated from the plurality of channel structures in a second direction perpendicular to the first direction, wherein resistivity of the second metal layer is less than resistivity of the first metal layer, wherein each of the plurality of gate electrodes further comprises a conductive barrier layer comprising a first portion arranged between a corresponding one of the plurality of insulating layers closest to each of the plurality of gate electrodes and the first metal layer and a second portion arranged between the corresponding one of the plurality of insulating layers and the second metal layer, and wherein the first portion of the conductive barrier layer and the second portion of the conductive barrier layer are continuous, wherein the conductive barrier layer electrically connects the first metal layer and the second metal layer, and wherein the second metal layer comprises aluminum or an alloy metal of copper and aluminum.

2 . The semiconductor device of claim 1 ,
wherein the conductive barrier layer further comprises a third portion arranged between the first metal layer and the second metal layer and continuous with the first portion and the second portion.

3 . The semiconductor device of claim 2 , wherein the second metal layer is separated from the first metal layer with the conductive barrier layer disposed therebetween.

4 . The semiconductor device of claim 1 , wherein each of the plurality of gate electrodes further comprises an insulating barrier layer that is in contact with the second metal layer and separated from the first metal layer.

5 . The semiconductor device of claim 4 , wherein the insulating barrier layer comprises aluminum oxide.

6 . The semiconductor device of claim 1 , wherein the second metal layer comprises an alloy metal of copper and aluminum having a copper to aluminum mass ratio of 9:1.

7 . The semiconductor device of claim 1 , wherein the first metal layer comprises tungsten, and a resistance of each of the plurality of gate electrodes is in a range of about 47% to about 60% of the resistance of the gate electrode if it included only tungsten.

8 . A semiconductor device comprising:
a plurality of gate stacks comprising a plurality of gate electrodes stacked on a substrate in a first direction perpendicular to an upper surface of the substrate, the plurality of gate stacks being separated from each other in a second direction parallel to the upper surface of the substrate; a plurality of insulating layers arranged between the plurality of gate electrodes; a plurality of channel structures passing through the plurality of gate stacks in the first direction; and an upper insulating layer comprising a portion thereof interposed between the plurality of gate stacks, wherein each of the plurality of gate electrodes comprises:
a first conductive layer arranged at a center of each of the plurality of gate stacks, wherein at least a pair of channel structures of the plurality of channel structures pass through the first conductive layer and the first conductive layer is continuous in the second direction at least between the pair of channel structures; and
second conductive layers arranged at respective edges of the plurality of gate stacks, the edges being parallel to a third direction perpendicular to each of the first and second directions, and the edges being separated from the portion of the upper insulating layer by the pair of channel structures,
wherein the first conductive layer comprises tungsten and the second conductive layers comprise a metal that is different from tungsten, and wherein a resistance of each of the plurality of gate electrodes is about 60% or less of a resistance of the gate electrode if it included only tungsten.

9 . The semiconductor device of claim 8 , wherein a sum of lengths of the second conductive layers of each of the plurality of gate electrodes in the second direction ranges from about 1/10 to about ⅕ of a length of corresponding one of the plurality of gate electrodes in the second direction.

10 . The semiconductor device of claim 8 , wherein
the second conductive layers comprise any one of copper, aluminum, and an alloy of copper and aluminum.

11 . The semiconductor device of claim 8 , wherein each of the plurality of gate electrodes further comprises a conductive barrier layer covering upper and lower surfaces of the first conductive layer,
wherein the conductive barrier layer comprises a portion thereof arranged between the first conductive layer and the second conductive layers.

12 . The semiconductor device of claim 8 , wherein each of the plurality of gate electrodes further comprises:
a first conductive barrier layer covering upper and lower surfaces of the first conductive layer; and a second conductive barrier layer covering upper and lower surfaces of a second conductive layer of the second conductive layers.

13 . The semiconductor device of claim 12 , wherein the first and second conductive barrier layers comprise different materials.

14 . The semiconductor device of claim 12 , wherein each of the first and second conductive barrier layers comprises a double layer of titanium and titanium nitride.

15 . The semiconductor device of claim 8 , wherein each of the plurality of gate electrodes further comprises an insulating barrier layer arranged between the portion of the upper insulating layer arranged between the plurality of gate stacks and a second conductive layer of the second conductive layers.

16 . The semiconductor device of claim 15 , wherein the insulating barrier layer is in contact with a portion of the upper insulating layer arranged between the plurality of gate stacks and a side surface of the second conductive layer, respectively.

17 . The semiconductor device of claim 15 , wherein the insulating barrier layer comprises aluminum oxide.

18 . The semiconductor device of claim 8 , wherein the resistance of each of the plurality of gate electrodes is in a range of about 47% to about 60% of the resistance of the gate electrode if it included only tungsten.

19 . A semiconductor device comprising:
a plurality of insulating layers stacked in a first direction; insulating barrier layers covering upper and lower surfaces of the plurality of insulating layers; a plurality of gate electrodes arranged between the plurality of insulating layers and partially filling a space between the plurality of insulating layers; a plurality of channel structures passing through the plurality of gate electrodes and the plurality of insulating layers in the first direction; and an upper insulating layer filling the space between the plurality of insulating layers, wherein each of the plurality of gate electrodes comprises: a first conductive layer comprising an inner wall and tungsten, the inner wall surrounding the plurality of channel structures; a second conductive layer arranged between the upper insulating layer and the first conductive layer and consisting of any one of copper, aluminum, and

Assignees

• Samsung Electronics Co Ltd

Inventors

• SONG Younggul
• Seok Junyeong
• Oh Eun Chu
• Jang Byungchul
• Lim Joonsung

Classifications

• H10D30/694

  characterised by the shapes, relative sizes or dispositions of the gate electrodes · CPC title

• H10D30/6891

  characterised by the shapes, relative sizes or dispositions of the floating gate electrode · CPC title

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H01L23/53238

  Electricity · mapped topic

• H01L23/53223

  Electricity · mapped topic