Vertical memory devices and methods of manufacturing the same

Patent metadata

Field	Value
Publication number	US-10079203-B2
Application number	US-201615271605-A
Country	US
Kind code	B2
Filing date	Sep 21, 2016
Priority date	Sep 23, 2015
Publication date	Sep 18, 2018
Grant date	Sep 18, 2018

Abstract

A vertical memory device includes a substrate, a plurality of channels on the substrate and extending in a vertical direction with respect to a top surface of the substrate, a plurality of non-metal gate patterns surrounding the channels and being stacked on top of each other and spaced apart from each other along the vertical direction, and a plurality of metal gate patterns stacked on top of each other. The metal gate patterns are spaced apart from each other along the vertical direction. Each of the metal gate patterns surrounds a corresponding one of the non-metal gate patterns.

First claim

What is claimed is:

1. A vertical memory device, comprising:
a substrate including a first region and a second region;
a plurality of channels on the first region of the substrate, the channels extending in a vertical direction with respect to a top surface of the substrate;
a plurality of non-metal gate patterns surrounding the channels, the plurality of non-metal gate patterns being stacked on top of each other on the first region of the substrate and spaced apart from each other along the vertical direction; and
a plurality of metal gate patterns stacked on top of each other on the second region of the substrate and spaced apart from each other along the vertical direction, each of the plurality of metal gate patterns surrounding a corresponding one of the plurality of non-metal gate patterns, wherein
the vertical memory device does not include any of the plurality of metal gate patterns on the first region of the substrate.

2. The vertical memory device of claim 1 , wherein the plurality of non-metal gate patterns include polysilicon.

3. The vertical memory device of claim 1 , wherein the plurality of metal gate patterns include at least one of a metal and a metal silicide.

4. The vertical memory device of claim 1 , wherein
the plurality of non-metal gate patterns and the plurality of metal gate patterns define a plurality of gate lines,
each of the gate lines includes one of the plurality of non-metal gate patterns and one of the plurality of metal gate patterns at a same level, and
the plurality of the gate lines are stacked on top of each other and spaced apart from each other along the vertical direction.

5. The vertical memory device of claim 4 , further comprising:
insulating interlayers between the plurality of gate lines,
wherein the insulating interlayers are stacked on top of each other and spaced apart from each other along the vertical direction.

6. The vertical memory device of claim 5 , further comprising:
interface layers surrounding the plurality of gate lines, wherein
the interface layers are between the insulating interlayers and the plurality of gate lines at each level.

7. The vertical memory device of claim 6 , wherein
the interface layers each include a first interface layer, a second interface layer on the first interface layer; and a third interface layer selectively surrounding one of the plurality of metal gate patterns,
the first interface layer and the second interface layer commonly surround one of the plurality of non-metal gate patterns and one of the plurality of metal gate patterns.

8. The vertical memory device of claim 7 , wherein
the first interface layer includes a metal oxide, and
the second interface layer and the third interface layer include a metal nitride.

9. The vertical memory device of claim 6 , wherein a space between the plurality of channels is fully filled with the interface layers and the plurality of non-metal gate patterns.

10. The vertical memory device of claim 4 , wherein
the plurality of gate lines are stacked in a stepped shape from the top surface of the substrate, and
the plurality of gate lines at each level includes a step portion protruding in a horizontal direction.

11. The vertical memory device of claim 10 , the step portion consists essentially of the plurality of metal gate patterns.

12. The vertical memory device of claim 11 , wherein the metal gate patterns include protrusions expanding in the vertical direction.

13. The vertical memory device of claim 11 , further comprising:
contacts electrically connected to the step portion of the plurality of gate lines at each level.

14. A vertical memory device, comprising:
a substrate;
insulating interlayers stacked on top of each other and spaced apart from each other along a vertical direction with respect to a top surface of the substrate;
a plurality of channels extending through the insulating interlayers in the vertical direction;
a plurality of non-metal gate patterns stacked on top of each other and spaced apart from each other along the vertical direction, the plurality of non-metal gate patterns partially filling gaps defined by the insulating interlayers and the plurality of channels, the gaps including spaces between the plurality of channels, the spaces being filled with the plurality of non-metal gate patterns; and
a plurality of metal gate patterns stacked on top of each other and spaced apart from each other along the vertical direction, the plurality of metal gate patterns partially filling remaining portions of the gaps such that the plurality of metal gate patterns are only disposed around the plurality of non-metal gate patterns and each one of the plurality of metal gate patterns is farther away from a nearest channel among the plurality of channels compared to a distance between an adjacent one of the plurality of non-metal gate patterns and the nearest channel.

15. The vertical memory device of claim 14 , wherein
the plurality of non-metal gate patterns are on a first region of the substrate and define channel holes,
the plurality of channels are arranged in an array on the first region of the substrate and extend through the channel holes,
the plurality of metal gate patterns are on a second region of the substrate,
the plurality of metal gate patterns extend from the plurality of non-metal gate patterns in a direction away from the array of the plurality of channels, and
the plurality of metal gate patterns are not arranged on the first region.

Assignees

• Son Yong Hoon
• Yeo Cha Dong
• Choi Han Mei
• Kim Kyung Hyun
• Nam Phil Ouk
• Park Kwang Chul
• Sohn Yeon Sil
• Lee Jin I
• Jung Won Bong
• Samsung Electronics Co Ltd

Inventors

• Son Yong-Hoon
• Yeo Cha-Dong
• Choi Han-Mei
• Kim Kyung-Hyun
• Nam Phil-Ouk
• Park Kwang-Chul
• Sohn Yeon-Sil
• Lee Jin-I
• Jung Won-Bong

Classifications

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/42 Primary

  Vias, e.g. via plugs · CPC title

• H01L27/11575

  Electricity · mapped topic

• H01L21/76816

  Electricity · mapped topic