Scalable patterning through layer expansion process and resulting structures

Patent metadata

Field	Value
Publication number	US-12532723-B2
Application number	US-202318361429-A
Country	US
Kind code	B2
Filing date	Jul 28, 2023
Priority date	Mar 30, 2021
Publication date	Jan 20, 2026
Grant date	Jan 20, 2026

Abstract

Small sized and closely pitched features can be formed by patterning a layer to have holes therein and then expanding the layer so that the holes shrink. If the expansion is sufficient to pinch off the respective holes, multiple holes can be formed from one larger hole. Holes smaller and of closer pitch than practical or possible may be obtained in this way. One process for expanding the layer includes implanting a dopant species having a larger average atomic spacing than does the material of the layer.

First claim

What is claimed is:

1 . A device comprising:
a structure; an etch stop layer over the structure; a first dielectric layer over the etch stop layer; a second dielectric layer over the first dielectric layer; an interface between the first dielectric layer and the second dielectric layer; a conductive via extending from a topmost surface of the second dielectric layer through the first dielectric layer and the etch stop layer, and electrically contacting the structure, the conductive via having a first width in the first dielectric layer and a second width, less than the first width, in the second dielectric layer and having an abrupt transition between the first width and the second width; and a dopant species in the second dielectric layer, wherein the second dielectric layer has a first average atomic spacing in a first region surrounding the conductive via and a second average atomic spacing, less than the first average atomic spacing, in a second region apart from the conductive via.

2 . The device of claim 1 , wherein the conductive via further has a third width, less than the first width and the second width, in the second dielectric layer and has a gradual transition from the second width to the third width.

3 . The device of claim 2 , wherein the third width is at an interface between the first dielectric layer and the second dielectric layer.

4 . The device of claim 1 , wherein the first region of the second dielectric layer is doped with a dopant species selected from the group consisting of Ge, Ar, Xe, Si, and combinations thereof.

5 . The device of claim 4 , the dopant species having an atomic radius at least as great as the atomic radius of silicon.

6 . The device of claim 1 , wherein the first region of the second dielectric layer includes a dopant species therein, and the second region of the second dielectric layer is free of the dopant species.

7 . The device of claim 6 , wherein a concentration of the dopant species decreases from a top surface of the second dielectric layer to a bottom surface of the second dielectric layer.

8 . A device comprising:
a structure; a first dielectric layer on the structure; a second dielectric layer on the first dielectric layer; a conductive via extending through the second dielectric layer and through the first dielectric layer and contacting the structure; wherein a first region of the second dielectric layer at least partially surrounds the conductive via and has a first average atomic spacing, and further wherein a second region of the second dielectric layer laterally surrounds the first region of the second dielectric layer and has a second average atomic spacing less than the first average atomic spacing; and wherein a cross-sectional width of the conductive via abruptly transitions from a first cross-sectional width value to a second greater cross-sectional width value at an interface between the first dielectric layer and the second dielectric layer.

9 . The device of claim 8 , wherein the first region of the second dielectric layer includes a dopant species therein, the dopant species having an atomic radius at least as great as the atomic radius of silicon.

10 . The device of claim 8 , wherein the concentration of dopant species in the second dielectric layer has a first value at the top of the second dielectric layer and has a second value at the bottom of the second dielectric layer, and wherein the concentration value transitions smoothly from the first value to the second value.

11 . The device of claim 8 , wherein:
the concentration of dopant species in the second dielectric has a first value at the top of the second dielectric layer and has a second value at the bottom of the second dielectric layer, and wherein the value transitions smoothly from the first value to the second value; and the cross-sectional width of the conductive via has a third cross-sectional width value at the top of the second dielectric layer, and wherein the cross-sectional width of the conductive via transitions smoothly from the first cross-sectional width value to the third cross-sectional width value.

12 . The device of claim 8 , wherein:
the concentration of dopant species in the second dielectric has a first concentration value at the top of the second dielectric layer and has a second concentration value at the bottom of the second dielectric layer, and wherein the concentration of dopant species transitions smoothly from the first concentration value to the second concentration value; the cross-sectional width of the conductive via has a third cross-sectional width value at the top of the second dielectric layer and, wherein the cross-sectional width of the conductive via transitions smoothly from the first cross-sectional width value to the third cross-sectional width value; and a ratio of the first concentration value to the second concentration value is equal to a ratio of the third cross-sectional width value to the first cross-sectional width value.

13 . The device of claim 12 , wherein the first concentration value is greater than the second concentration value.

14 . The device of claim 12 , wherein the conductive via is vertically mis-aligned to the structure at the region of the conductive via having the third cross-sectional width value, and is vertically aligned with the structure at the region of the conductive via having the second cross-sectional width value.

15 . The device of claim 12 , wherein the conductive via is vertically mis-aligned to the structure at the region of the conductive via having the third cross-sectional width value and the region of the conductive via having the first cross-sectional width value, and is vertically aligned with the structure at the region of the conductive via having the second cross-sectional width value.

16 . The device of claim 12 , wherein the structure is a terminal selected from the group consisting of a transistor gate contact, a transistor source contact, and a transistor drain contact.

17 . The device of claim 12 , wherein the second dielectric layer comprises silicon oxide.

18 . A device comprising:
a contact structure embedded in a dielectric layer; a conductive via physically contacting the contact structure, the conductive via being embedded in at least one first dielectric layer and at least one second dielectric layer, the conductive via having a first cross-sectional width value at an interface between the first at least one dielectric layer and the second at least one dielectric layer, having a second cross-sectional width value greater than the first cross-sectional width value at an interface between the first at least one dielectric layer and the contact structure, and having a third cross-sectional width value less than the first cross-sectional width value at a top of the second at least one dielectric layer, the cross-sectional width of the conductive via transitioning smoothly from the first cross-sectional width value to the third cross-sectional width value and transitioning abruptly from the first cross-sectional width value to the second cross-sectional width value; and wherein an average atomic spacing of the second at least one dielectric layer has a first average atomic spacing value at the interface between the second at least one dielectric layer and the first at least one dielectric layer and has a second average atomic spacing value less than the first average atomic spacing value at the top of the second at least one dielectric layer, the average atomic spacing of the second

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• LEE Kai-Hsuan
• Yeong Sai-Hooi
• Chui Chi On

Classifications

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/095 Primary

  by irradiating with electromagnetic or particle radiation (plasma treatment H10W20/096) · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10D84/0149

  Manufacturing their interconnections or electrodes, e.g. source or drain electrodes · CPC title

• H10W20/081 Primary

  by forming openings in the dielectric parts · CPC title