Metal heterojunction structure with capping metal layer

US2020098591A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2020098591-A1
Application numberUS-201916400620-A
CountryUS
Kind codeA1
Filing dateMay 1, 2019
Priority dateSep 26, 2018
Publication dateMar 26, 2020
Grant date

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

The current disclosure describes techniques of protecting a metal interconnect structure from being damaged by subsequent chemical mechanical polishing processes used for forming other metal structures over the metal interconnect structure. The metal interconnect structure is receded to form a recess between the metal interconnect structure and the surrounding dielectric layer. A metal cap structure is formed within the recess. An upper portion of the dielectric layer is strained to include a tensile stress which expands the dielectric layer against the metal cap structure to reduce or eliminate a gap in the interface between the metal cap structure and the dielectric layer.

First claim

Opening claim text (preview).

1 . A semiconductor structure, comprising: a substrate; a semiconductor device over the substrate; a first interconnect structure within a first dielectric layer and connecting to a terminal of the semiconductor device; a first cap structure over the first interconnect structure and contacting the first interconnect structure, the first cap structure at least partially within the first dielectric layer; and a second interconnect structure over the first cap structure and contacting the first cap structure. 2 . The semiconductor structure of claim 1 , wherein an upper portion of the first dielectric layer includes a tensile stress against an interface between the first dielectric layer and the first cap structure. 3 . The semiconductor structure of claim 2 , wherein the first cap structure is at least partially within the upper portion of the first dielectric layer. 4 . The semiconductor structure of claim 2 , wherein the upper portion of the first dielectric layer includes one or more of germanium, silicon, carbon, nitrogen, phosphorus or boron. 5 . The semiconductor structure of claim 1 , wherein the first cap structure includes a same conductive material as the second interconnect structure. 6 . The semiconductor structure of claim 1 , wherein the first cap structure includes a different conductive material from the first interconnect structure. 7 . The semiconductor structure of claim 6 , wherein a conductive material of the first cap structure is different from a conductive material of the first interconnect structure in reacting to at least one of an acidic solution or an alkaline solution. 8 . The semiconductor structure of claim 6 , wherein one of the first cap structure or the first interconnect structure is tungsten and another one of the first cap structure or the first interconnect structure is one or more of cobalt or copper. 9 . The semiconductor structure of claim 1 , wherein the first cap structure extends laterally beyond the second interconnect structure at least in one direction. 10 . The semiconductor structure of claim 1 , wherein the first cap structure includes a different diameter than the second interconnect structure. 11 . The semiconductor structure of claim 1 , wherein the first cap structure misaligns with the second interconnect structure. 12 . The semiconductor structure of claim 1 , further comprising a second cap structure directly over the second interconnect structure and a third interconnect structure directly over the second cap structure. 13 . A semiconductor structure, comprising: a substrate; a dielectric layer over the substrate; an conductive via structure within the dielectric layer, an upper surface of the conductive via structure being lower than an upper surface of the dielectric layer adjacent to the conductive via structure; and a conductive cap structure directly over the conductive via structure, an upper surface of the conductive cap structure being one of substantially at a same level with or higher than the upper surface of the dielectric layer adjacent to the conductive via structure. 14 . The semiconductor structure of claim 13 , wherein the conductive cap structure extends laterally beyond the conductive via structure at least in one direction. 15 . The semiconductor structure of claim 13 , wherein the conductive cap structure misaligns with the conductive via structure. 16 . A method, comprising: forming a first metal structure within a first dielectric layer, an upper surface of the first metal structure being lower than an upper surface of the first dielectric layer that is adjacent to the upper surface of the first metal structure; forming a second metal structure over the upper surface of the first metal structure; and straining an upper portion of the first dielectric layer to have a tensile stress. 17 . The method of claim 16 , wherein the straining including implanting ions of one or more of germanium, silicon, carbon, nitrogen, phosphorus or boron into the upper portion of the first dielectric layer. 18 . The method of claim 16 , further comprising forming a third metal structure directly over the second metal structure, the third metal structure being surrounded by a second dielectric layer. 19 . The method of claim 16 , wherein the forming the first metal structure within the first dielectric layer includes forming a recess portion between the first dielectric layer and the first metal structure by removing an upper portion of the first metal structure. 20 . The method of claim 16 , wherein the straining an upper portion of the first dielectric layer increases a volume of the upper portion of the first dielectric layer.

Assignees

Inventors

Classifications

  • the principal metal being a transition metal · CPC title

  • containing abrasives or grinding agents {(abrasives as such C09K3/14; polishing of semi-conductors H10P52/40)} · CPC title

  • the principal metal being a refractory metal · CPC title

  • the principal metal being copper · CPC title

  • based on metals, e.g. alloys, metal silicides (H10W20/4484 takes precedence) · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US2020098591A1 cover?
The current disclosure describes techniques of protecting a metal interconnect structure from being damaged by subsequent chemical mechanical polishing processes used for forming other metal structures over the metal interconnect structure. The metal interconnect structure is receded to form a recess between the metal interconnect structure and the surrounding dielectric layer. A metal cap stru…
Who is the assignee on this patent?
Taiwan Semiconductor Mfg Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10W20/0698. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Mar 26 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).