Metal Loss Prevention Using Implantation

Patent metadata

Field	Value
Publication number	US-2019371664-A1
Application number	US-201815993768-A
Country	US
Kind code	A1
Filing date	May 31, 2018
Priority date	May 31, 2018
Publication date	Dec 5, 2019
Grant date	—

Abstract

The present disclosure provides methods for forming conductive features in a dielectric layer without using adhesion layers or barrier layers and devices formed thereby. In some embodiments, a structure comprising a dielectric layer over a substrate, and a conductive feature disposed through the dielectric layer. The dielectric layer has a lower surface near the substrate and a top surface distal from the substrate. The conductive feature is in direct contact with the dielectric layer, and the dielectric layer comprises an implant species. A concentration of the implant species in the dielectric layer has a peak concentration proximate the top surface of the dielectric layer, and the concentration of the implant species decreases from the peak concentration in a direction towards the lower surface of the dielectric layer.

First claim

1 .- 6 . (canceled)

7 . A method for semiconductor processing, the method comprising:
depositing a conductive feature in a dielectric layer, wherein the conductive feature is in direct contact with the dielectric layer; after depositing the conductive feature, implanting an implant species into the dielectric layer; and after implanting the implant species, removing a portion of the conductive feature by a first planarization process.

8 . The method of claim 7 , wherein the implant species comprises at least one of Geranium (Ge), Silicon (Si), and Nitrogen (N).

9 . The method of claim 7 , wherein implanting the implant species comprises expanding the dielectric layer to form an expanded dielectric layer, the expanded dielectric layer applying a compressive force to the conductive feature.

10 . The method of claim 7 , wherein a peak concentration point of the implant species in the dielectric layer is in a portion of the dielectric layer removed by the first planarization process.

11 . The method of claim 7 , further comprising forming an opening through the dielectric layer to expose a conductive material in a layer under the dielectric layer, wherein depositing the conductive feature comprises growing the conductive feature in the opening in a bottom-up manner.

12 . The method of claim 7 , further comprising:
after removing the portion of the conductive feature, implanting another implant species into the dielectric layer; and after implanting the another implant species, removing another portion of the conductive feature and the dielectric layer by a second planarization process.

13 . The method of claim 12 , wherein implanting the implant species into the dielectric layer is performed at an angle from an axis that is perpendicular to a surface of the dielectric layer, the angle being greater than zero.

14 . A method for semiconductor processing, the method comprising:
depositing a dielectric material over a substrate having a conductive material; forming an opening in the dielectric material to expose the conductive material; depositing a conductive feature in the opening and directly contacting the conductive material; performing a first implantation process to implant an implant species in the dielectric material; and after performing the first implantation process, performing a first planarization process to remove a portion of the conductive feature.

15 . The method of claim 14 , wherein depositing the conductive feature comprises growing the conductive feature in the opening in a bottom-up manner.

16 . The method of claim 14 , wherein the dielectric material comprises an etch stop layer and an interlayer dielectric above the etch stop layer.

17 . The method of claim 14 , wherein implanting the implant species comprises implanting a neutral element in the dielectric material to expand the dielectric material to apply compression around the conductive feature.

18 . The method of claim 14 , wherein performing the first implantation process comprises directing the implant species towards the dielectric material at a non-zero angle relative to an axis perpendicular to a surface of the dielectric material, the surface of the dielectric material being distal from the substrate.

19 . The method of claim 14 , wherein depositing the conductive feature forms an overfill portion above the dielectric material, and performing the first planarization process removes the overfill portion of the conductive material.

20 . The method of claim 19 , further comprising:
after performing the first planarization process, performing a second implantation process to implant another implant species in the dielectric material; and after performing the second implantation process, performing a second planarization process to remove a portion of the dielectric material and a portion of the conductive material.

21 . A method for semiconductor processing, the method comprising:
depositing a dielectric material over a substrate; forming an opening in the dielectric material to expose a conductive feature; filling the opening with a conductive material, wherein a gap is interposed between the conductive material and a sidewall of the opening; performing a first implantation process to implant an implant species in the dielectric material, wherein a width of the gap decreases after performing the first implantation process; and after performing the first implantation process, performing a first planarization process to remove a portion of the conductive material.

22 . The method of claim 21 , wherein the implant species comprises Geranium (Ge), Silicon (Si), or Nitrogen (N).

23 . The method of claim 21 , wherein a peak concentration of the implant species is in a range from 8×10 18 atoms/cm 3 to 1×10 21 atoms/cm 3 .

24 . The method of claim 21 , further comprising forming an etch stop layer over the substrate, wherein the dielectric material is deposited over the etch stop layer, wherein the conductive material is disposed through the etch stop layer.

25 . The method of claim 24 , wherein the etch stop layer comprises the implant species, a concentration of the implant species in the etch stop layer being in a range from about 2×10 18 atoms/cm 3 to about 6×10 20 atoms/cm 3 .

26 . The method of claim 21 , wherein the dielectric material comprises a silicon oxide, silicon oxynitride, silicon oxycarbide, or a combination thereof.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wu Li-Chieh
• Chang Tang-Kuei
• Wei Kuo-Hsiu
• Chen Kei-Wei
• Wang Ying-Lang
• Liu Su-Hao
• Chen Kuo-Ju
• Chen Liang-Yin
• Chang Huicheng
• Chang Ting-Kui
• Lee Chia Hsuan

Classifications

• H10P30/40

  into insulating materials · CPC title

• H10W20/081

  by forming openings in the dielectric parts · CPC title

• H10W20/064

  by modifying the conductivity of conductive parts, e.g. by alloying · CPC title

• H10W20/48

  Insulating materials thereof · CPC title

• H10W20/47

  comprising two or more dielectric layers having different properties, e.g. different dielectric constants · CPC title