Semiconductor memory device and fabrication method thereof
US-2023039408-A1 · Feb 9, 2023 · US
Semiconductor device and fabrication method thereof
US12532476B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-12532476-B2 |
| Application number | US-202217994401-A |
| Country | US |
| Kind code | B2 |
| Filing date | Nov 28, 2022 |
| Priority date | Nov 7, 2022 |
| Publication date | Jan 20, 2026 |
| Grant date | Jan 20, 2026 |
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- Title
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Abstract
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A semiconductor device includes a substrate having a flash memory region and a logic device region, a logic transistor disposed in the logic device region, and a flash memory transistor disposed in the flash memory region. The flash memory transistor includes a metal select gate having two opposite sidewalls and two memory gates disposed on the two opposite sidewalls of the metal select gate.
First claim
Opening claim text (preview).
What is claimed is: 1 . A semiconductor device, comprising: a substrate having a flash memory region and a logic device region; at least one logic transistor disposed in the logic device region; and at least one flash memory transistor disposed in the flash memory region, wherein the flash memory transistor comprises a metal select gate having two opposite sidewalls and two memory gates respectively disposed on the two opposite sidewalls of the metal select gate; and two charge storage structures respectively disposed between the two memory gates and the substrate, wherein each of the two charge storage structures has an L-shaped profile, wherein the metal select gate comprises a high-k gate dielectric layer in direct contact with the two charge storage structures. 2 . The semiconductor device according to claim 1 , wherein the at least one logic transistor comprises a metal gate. 3 . The semiconductor device according to claim 2 , wherein the metal gate and the metal select gate have the same gate structure. 4 . The semiconductor device according to claim 2 , wherein each of the metal gate and the metal select gate comprises a conductive gate electrode. 5 . The semiconductor device according to claim 2 , wherein a top surface of the metal gate is coplanar with a top surface of the metal select gate. 6 . The semiconductor device according to claim 1 further comprising: a dielectric layer on the substrate and covering the metal select gate. 7 . The semiconductor device according to claim 1 , wherein each of the two charge storage structures comprises an oxide-nitride-oxide (ONO) storage structure. 8 . The semiconductor device according to claim 6 , wherein each of the two charge storage structures comprises a side surface, and the dielectric layer is in direct contact with the side surface. 9 . The semiconductor device according to claim 1 , wherein the two memory gates are polysilicon gates. 10 . The semiconductor device according to claim 1 further comprising: two source/drain doping regions in the substrate and adjacent to the two memory gates, respectively.
Assignees
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Classifications
with source and drain on different levels, e.g. with sloping channels · CPC title
with a cell select transistor, e.g. NAND · CPC title
with source and drain on different levels, e.g. with sloping channels · CPC title
having at least one additional gate, e.g. program gate, erase gate or select gate · CPC title
comprising charge-trapping insulators · CPC title
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Frequently asked questions
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- What does patent US12532476B2 cover?
- A semiconductor device includes a substrate having a flash memory region and a logic device region, a logic transistor disposed in the logic device region, and a flash memory transistor disposed in the flash memory region. The flash memory transistor includes a metal select gate having two opposite sidewalls and two memory gates disposed on the two opposite sidewalls of the metal select gate.
- Who is the assignee on this patent?
- United Microelectronics Corp
- What technology area does this patent fall under?
- Primary CPC classification H10B43/35. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Jan 20 2026 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 4 related publications on this page (citations in our corpus or others sharing the same primary CPC).