Variable resistance memory device

Patent metadata

Field	Value
Publication number	US-12527239-B2
Application number	US-202217989085-A
Country	US
Kind code	B2
Filing date	Nov 17, 2022
Priority date	Dec 27, 2019
Publication date	Jan 13, 2026
Grant date	Jan 13, 2026

Abstract

A variable resistance memory device includes a variable resistance layer, a first conductive element, and a second conductive element. The variable resistance layer includes a first layer and a second layer. The first layer is formed of a first material. The second layer is on the first layer and formed of a second material having a density different from a density of the first material. The first conductive element and a second conductive element are located on the variable resistance layer and spaced apart from each other in order to form a current path in the variable resistance layer. The current path is in a direction perpendicular to a direction in which the first layer and the second layer are stacked.

First claim

What is claimed is:

1 . A variable resistance memory device comprising:
a substrate; and a plurality of cell strings on the substrate, each extending in a first direction perpendicular to a surface of the substrate; wherein each of the plurality of cell strings comprises: an insulating layer extending in the first direction; a variable resistance layer extending in the first direction and surrounding the insulating layer, the variable resistance layer including a first layer formed of a first material, a second layer formed of a second material, and a third layer formed of a third material, which are stacked in a second direction perpendicular to the first direction; a channel layer extending in the first direction and surrounding the variable resistance layer; and a plurality of gate electrodes spaced apart from each other along the first direction and surrounding the channel layer, wherein the second layer is between the first laver and the third laver, the third laver is between the second layer and the channel layer, a density of the second material is higher than a density of the first material, and a density of the third material is lower than the density of the second material.

2 . The variable resistance memory device of claim 1 , wherein each of the first material, the second material and the third material independently is any one of Rb 2 O, TiO 2 , BaO, ZrO 2 , CaO, HfO 2 , SrO, Sc 2 O 3 , MgO, Li 2 O, Al 2 O 3 , SiO 2 , BeO, Nb 2 O 5 , NiO, Ta 2 O 5 , WO 3 , V 2 O 5 , La 2 O 3 , Gd 2 O 3 , CuO, MoO 3 , Cr 2 O 3 , and MnO 2 .

3 . The variable resistance memory device of claim 1 , wherein
the first material and the second material have a same valence, and a density difference between the first material and the second material is greater than 1.5 g/cm 3 .

4 . The variable resistance memory device of claim 1 , wherein
the first material and the second material have a same valence, the first material and the third material are a same one of TiO 2 , MnO 2 , ZrO 2 , SiO 2 , Cr 2 O 3 , La 2 O 3 , SrO, CaO, BeO, MoO 3 , and the second material is one of Hf 2 , Gd 2 O 3 , NiO, and WO 3 .

5 . The variable resistance memory device of claim 1 , wherein a density difference between the first material and the second material is greater than 1 g/cm 3 and less than 8 g/cm 3 .

6 . The variable resistance memory device of claim 1 , wherein a density difference between the second material and the third material is greater than 1 g/cm 3 and less than 8 g/cm 3 .

7 . The variable resistance memory device of claim 1 , wherein the first material and the third material are a same material.

8 . The variable resistance memory device of claim 1 , wherein
a thickness of the second layer is less than a thickness of the first layer, and the thickness of the second layer is less than a thickness of the third layer.

9 . The variable resistance memory device of claim 1 , wherein each of the first material and the second material is an oxide having a bandgap energy of 2 eV or more.

10 . The variable resistance memory device of claim 1 , wherein a thickness of each of the first layer, the second layer, and the third layer is equal to or less than 10 nm.

11 . The variable resistance memory device of claim 10 , wherein the second layer has a thickness equal to or less than 2 nm.

12 . The variable resistance memory device of claim 10 , wherein the third layer contacts the channel layer and has a thickness equal to or greater than 5 nm.

13 . The variable resistance memory device of claim 1 , wherein the plurality of cell strings each have a cylindrical pillar shape.

14 . The variable resistance memory device of claim 1 , further comprising:
a source region and a drain region contacting opposite end portion of the channel layer in the first direction, respectively.

15 . The variable resistance memory device of claim 14 , further comprising:
a bit line connected to the drain region; a source line connected to the source region; and a plurality of word lines connected to the plurality of gate electrodes, respectively.

16 . A variable resistance memory device comprising:
a substrate; and a plurality of cell strings on the substrate, each extending in a first direction perpendicular to a surface of the substrate; wherein each of the plurality of cell strings comprises: an insulating layer extending in the first direction; a variable resistance layer extending in the first direction and surrounding the insulating layer, the variable resistance layer including a first layer formed of a first material and a second layer formed of a second material, which are stacked in a second direction perpendicular to the first direction; a channel layer extending in the first direction and surrounding the variable resistance layer; a plurality of gate electrodes alternately arranged and spaced apart from each other along the first direction and surrounding the channel layer, wherein the first material is HfO 2 and the second material is MnO 2 , ZrO 2 , SiO 2 , or Cr 2 O 3 , the first material is Gd 2 O 3 and the second material is Cr 2 O 3 or La 2 O 3 , the first material is NiO and the second material is SrO, CaO, or BeO, or the first material is WO 3 and the second material is MoO 3 .

17 . The variable resistance memory device of claim 16 , wherein
the first material is HfD 2 , and the second material is MnO 2 , ZrO 2 , SiO 2 , or Cr 2 O 3 .

18 . The variable resistance memory device of claim 16 , wherein
the first material is Gd 2 O 3 , and the second material is Cr 2 O 3 or La 2 O 3 .

19 . The variable resistance memory device of claim 16 , wherein
the first material is NiO, and the second material is SrO, CaO, or BeO.

20 . The variable resistance memory device of claim 16 , wherein
the first material is WO 3 , and the second material is MoO 3 .

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Seyun
• Kim Jinhong
• Mizusaki Soichiro
• Yoon Jungho
• Cho Youngjin

Classifications

• H10N70/24

  based on migration or redistribution of ionic species, e.g. anions, vacancies · CPC title

• H10B63/84

  arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays · CPC title

• H10B63/82

  the switching components having a common active material layer · CPC title

• H10B63/34 Primary

  of the vertical channel field-effect transistor type · CPC title

• H10B63/30

  comprising selection components having three or more electrodes, e.g. transistors · CPC title