Direct bonding and debonding of carrier

Patent metadata

Field	Value
Publication number	US-12525572-B2
Application number	US-202217708716-A
Country	US
Kind code	B2
Filing date	Mar 30, 2022
Priority date	Mar 31, 2021
Publication date	Jan 13, 2026
Grant date	Jan 13, 2026

Abstract

A method of processing a semiconductor element is disclosed. The method can include providing the semiconductor element that has a first nonconductive material. The first nonconductive material is disposed on a device portion of the semiconductor element. The method can include providing a transparent carrier. The method can include providing an intervening structure that has a second nonconductive material, a photolysis layer, and an opaque layer stacked together. The method can include forming a bonded structure such that the second nonconductive material is directly bonded to the first nonconductive material or to the transparent carrier. The intervening structure is disposed between the semiconductor element and the transparent carrier. The method can include decoupling the transparent carrier from the semiconductor element by exposing the photolysis layer to light through the transparent carrier such that the light decomposes the photolysis layer.

First claim

What is claimed is:

1 . A method of processing a semiconductor element comprising:
providing the semiconductor element having a first nonconductive material, the first nonconductive material disposed on a device portion of the semiconductor element; providing a transparent carrier; providing an intervening structure having a second nonconductive material, a photolysis layer, and an opaque layer stacked together; forming a bonded structure such that the second nonconductive material is directly bonded to the first nonconductive material or to the transparent carrier, the intervening structure being disposed between the semiconductor element and the transparent carrier; and decoupling the transparent carrier from the semiconductor element by exposing the photolysis layer to light through the transparent carrier such that the light decomposes the photolysis layer.

2 . The method of claim 1 , further comprising processing the semiconductor element after forming the bonded structure and before decoupling the transparent carrier from the semiconductor element, the processing includes polishing a portion of the semiconductor element by way of chemical mechanical polishing.

3 . The method of claim 2 , wherein the processing includes forming a nonconductive layer such that the device portion of the semiconductor element is disposed between the first nonconductive material and the nonconductive layer, and forming a conductive feature in or with the nonconductive layer.

4 . The method of claim 1 , wherein the opaque layer is disposed between the second nonconductive material and the photolysis layer, the method comprising directly bonding the second nonconductive material to the first nonconductive material.

5 . The method of claim 4 , wherein the intervening structure is disposed on the transparent carrier prior to the bonding.

6 . The method of claim 1 , wherein the photolysis layer is disposed between the second nonconductive material and the opaque layer.

7 . The method of claim 6 , wherein the intervening structure further comprises an adhesion layer between the second nonconductive material and the photolysis layer.

8 . The method of claim 1 , wherein the light comprises a UV laser.

9 . The method of claim 1 , wherein the photolysis layer comprises a photolysis polymer layer.

10 . The method of claim 1 , wherein the opaque layer comprises a metal layer.

11 . The method of claim 10 , wherein a surface of the metal layer that faces the transparent layer comprises a reflective surface.

12 . The method of claim 10 , wherein the metal layer comprises titanium, and the metal layer has a thickness in a range of 20 nm to 100 nm.

13 . The method of claim 1 , further comprising removing a portion of the semiconductor element from a side of the semiconductor element that faces away the transparent layer, the removing comprises grinding, wet chemical etching, dry etching, plasma etching, or polishing.

14 . The method of claim 13 , wherein the removing comprises thinning the semiconductor element to a thickness of less than 100 μm, and to have a total thickness variation of 5 μm or less.

15 . The method of claim 1 , further comprising directly bonding a second semiconductor element to the semiconductor element such that the semiconductor element is disposed between the intervening layer and the second semiconductor element.

16 . The method of claim 15 , wherein the directly bonding comprises directly bonding the first nonconductive material to a third nonconductive material of the second semiconductor element, and directly bonding a first conductive feature of the semiconductor element to a second conductive feature of the second semiconductor element.

17 . The method of claim 15 , further comprising directly bonding a second intervening layer to the second semiconductor element and bonding a second transparent layer to the intervening layer such that the intervening layer is disposed between the second semiconductor element and the second transparent layer.

18 . The method of claim 1 further comprising bonding the semiconductor element to a dicing frame such that the semiconductor element is disposed between the transparent carrier and the dicing frame, singulating the semiconductor element into a plurality of singulated integrated device dies, wherein the semiconductor element comprises a semiconductor wafer.

19 . The method of claim 1 , wherein the first nonconductive material comprises a dielectric layer, the second nonconductive material comprises a silicon oxide layer, and the transparent layer comprises a glass carrier wafer.

20 . The method of claim 1 , further comprising removing the opaque layer.

21 . The method of claim 1 , wherein the photolysis layer has a thickness in a range of 100 nm to 1 μm.

22 . The method of claim 1 , further comprising coupling the semiconductor element to an adaptor plate, and removing the second nonconductive material, wherein the semiconductor element and the adaptor plate are coupled after forming the bonded structure, and the second nonconductive material is removed after decoupling the transparent carrier from the semiconductor element.

23 . The method of claim 22 , further comprising, after removing the second nonconductive material, polishing the semiconductor element for direct bonding by way of chemical mechanical polishing.

24 . A method of processing a semiconductor element comprising:
providing a carrier structure having a first side and a second side opposite the first side, the carrier structure including a transparent carrier positioned closer to the first side than to the second side and a photolysis layer positioned between the transparent carrier and the second side; bonding a device die to the second side of the carrier structure; providing a molding material at least partially over the device die; and removing the transparent carrier by exposing the photolysis layer to light through the transparent carrier such that the light decomposes the photolysis layer.

25 . The method of claim 24 , wherein the carrier structure further including a nonconductive layer that at least partially defines the second side and an opaque layer between the photolysis layer and the nonconductive layer wherein the device dies are directly bonded to the nonconductive layer without an intervening adhesive, the transparent carrier at least partially defines the first side of the carrier structure.

26 . The method of claim 25 , further comprising, after removing the transparent carrier, removing the opaque layer and the nonconductive layer to thereby form a reconstituted wafer, and comprising forming a redistribution layer on the reconstituted wafer.

27 . A method of processing a semiconductor element comprising:
providing a first bonded structure having a first semiconductor element on a first carrier structure, the first semiconductor element having a first side on the first carrier structure and a second side opposite the first side; thinning the first semiconductor element from the second side of the first semiconductor element while the first semiconductor element is on the first carrier structure; providing a second bonded structure having a second semiconductor element on a second carrier structure, the second semiconductor element having a first side on the second carrier structure and a second side opp

Assignees

• Adeia Semiconductor Bonding Technologies Inc

Inventors

• Gao Guilian
• Fountain Jr Gaius Gillman

Classifications

• H10P72/745

  the bond interface between the auxiliary support and the wafer comprises three or more layers · CPC title

• H10W72/944

  Dispositions of multiple bond pads · CPC title

• H10W72/01904

  using temporary auxiliary members, e.g. using sacrificial coatings or handle substrates · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W80/312

  characterised by the direct bonding of electrically conductive pads · CPC title