Microelectronic assemblies including stacked dies coupled by a through dielectric via

Patent metadata

Field	Value
Publication number	US-12525563-B2
Application number	US-202217854613-A
Country	US
Kind code	B2
Filing date	Jun 30, 2022
Priority date	Jun 30, 2022
Publication date	Jan 13, 2026
Grant date	Jan 13, 2026

Abstract

Disclosed herein are microelectronic assemblies, as well as related apparatuses and methods. In some embodiments, a microelectronic assembly may include a plurality of dies stacked vertically; a trench of dielectric material extending through the plurality of dies; a conductive via extending through the trench of dielectric material; and a plurality of conductive pathways between the plurality of dies and the conductive via, wherein individual ones of the conductive pathways are electrically coupled to the conductive via and to individual ones of the plurality of dies, and wherein the individual ones of the plurality of conductive pathways have a first portion including a first material and a second portion including a second material different from the first material.

First claim

The invention claimed is:

1 . A microelectronic assembly, comprising:
a plurality of dies stacked vertically; a trench of dielectric material extending through the plurality of dies; a conductive via extending through the trench of dielectric material; and a plurality of conductive pathways between the plurality of dies and the conductive via, wherein individual ones of the conductive pathways are electrically coupled to the conductive via and to individual ones of the plurality of dies, and wherein the individual ones of the plurality of conductive pathways have a first portion including a first material and a second portion including a second material different from the first material.

2 . The microelectronic assembly of claim 1 , wherein the first material includes one or more of copper and aluminum.

3 . The microelectronic assembly of claim 1 , wherein the second material includes one or more of tungsten, ruthenium, or molybdenum.

4 . The microelectronic assembly of claim 1 , wherein the second portion of an individual one of the plurality of conductive pathways extends at least partially on the first portion.

5 . The microelectronic assembly of claim 1 , wherein the dielectric material includes silicon and one or more of nitrogen, oxygen, and carbon; a polyimide material; or a low-k or ultra low-k dielectric.

6 . The microelectronic assembly of claim 1 , wherein a material of the conductive via includes one or more of copper, nickel, molybdenum, ruthenium, cobalt, polysilicon, or tungsten.

7 . The microelectronic assembly of claim 1 , wherein a cross-section dimension of the conductive via is between 40 nanometers and 10 microns.

8 . The microelectronic assembly of claim 1 , wherein the plurality of vertically stacked dies has a first surface and a second surface opposite the first surface, and the microelectronic assembly further including:
a base die at the first surface of the plurality of vertically stacked dies, the base die electrically coupled to the conductive via.

9 . The microelectronic assembly of claim 8 , wherein the base die is a controller die with logic elements, and the plurality of vertically stacked dies are memory dies.

10 . The microelectronic assembly of claim 8 , wherein the base die is a first base die, and the microelectronic assembly further including:
a second base die at the second surface of the plurality of vertically stacked dies, the second base die electrically coupled to the conductive via.

11 . The microelectronic assembly of claim 8 , wherein the base die includes a first surface and an opposing second surface, wherein the plurality of vertically stacked dies is at the second surface of the base die, and the microelectronic assembly further including:
a package substrate electrically coupled to the first surface of the base die.

12 . A microelectronic assembly, comprising:
a plurality of vertically stacked dies; a trench of dielectric material through the plurality of vertically stacked dies; a first conductive via extending through the trench of dielectric material; a plurality of first conductive pathways between the plurality of vertically stacked dies and the first conductive via, wherein individual ones of the plurality of first conductive pathways are electrically coupled to individual ones of the plurality of vertically stacked dies and to the first conductive via, and wherein the individual ones of the plurality of first conductive pathways have a first portion including a first material and a second portion including a second material different from the first material; a second conductive via extending through the trench of dielectric material; and a plurality of second conductive pathways between the plurality of vertically stacked dies and the second conductive via, wherein individual ones of the plurality of second conductive pathways are electrically coupled to individual ones of the plurality of vertically stacked dies and to the second conductive via, and wherein the individual ones of the plurality of second conductive pathways have a third portion including a third material and a fourth portion including the second material.

13 . The microelectronic assembly of claim 12 , wherein the first portion is electrically coupled to the plurality of vertically stacked dies, and wherein the first material includes one or more of copper and aluminum.

14 . The microelectronic assembly of claim 12 , wherein the second portion is electrically coupled to the first conductive via, and wherein the second material includes one or more of tungsten, ruthenium, or molybdenum.

15 . The microelectronic assembly of claim 12 , wherein the third portion is electrically coupled to the plurality of vertically stacked dies, and wherein the third material includes one or more of copper and aluminum.

16 . The microelectronic assembly of claim 12 , wherein the fourth portion is electrically coupled to the second conductive via, and wherein the second material includes one or more of tungsten, ruthenium, or molybdenum.

17 . A microelectronic assembly, comprising:
a plurality of vertically stacked dies; a trench of dielectric material through the plurality of vertically stacked dies; a plurality of conductive vias extending through the trench of dielectric material; and a plurality of conductive pathways between the plurality of vertically stacked dies and the plurality of conductive vias, wherein individual ones of the plurality of conductive pathways are electrically coupled to individual ones of the plurality of vertically stacked dies and to individual ones of the plurality of conductive vias, and wherein the individual ones of the plurality of conductive pathways have a first portion including a first material and a second portion including a second material different from the first material.

18 . The microelectronic assembly of claim 17 , wherein the plurality of vertically stacked dies includes between 2 and 32 dies.

19 . The microelectronic assembly of claim 17 , wherein the plurality of vertically stacked dies includes between 32 and 128 dies.

20 . The microelectronic assembly of claim 17 , wherein the trench of dielectric material is one of a plurality of trenches of dielectric material through the plurality of vertically stacked dies.

Assignees

• Intel Corp

Inventors

• Morein Stephen
• Mahajan Ravindranath Vithal
• Majhi Prashant

Classifications

• H10W72/30

  Die-attach connectors · CPC title

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title

• H10W72/851

  Dispositions of multiple connectors or interconnections · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title