Three-dimensional memory devices and methods for forming the same

Patent metadata

Field	Value
Publication number	US-12525558-B2
Application number	US-202117480897-A
Country	US
Kind code	B2
Filing date	Sep 21, 2021
Priority date	Jun 30, 2021
Publication date	Jan 13, 2026
Grant date	Jan 13, 2026

Abstract

In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, a third semiconductor structure, a first bonding interface between the first semiconductor structure and the second semiconductor structure, and a second bonding interface between the second semiconductor structure and the third semiconductor structure. The first semiconductor structure includes an array of NAND memory strings and a first semiconductor layer in contact with sources of the array of NAND memory strings. The second semiconductor structure includes a first peripheral circuit of the array of NAND memory strings including a first transistor, and a second semiconductor layer in contact with the first transistor. A third semiconductor structure includes a second peripheral circuit of the array of NAND memory strings including a second transistor, and a third semiconductor layer in contact with the second transistor. The first peripheral circuit is between the first bonding interface and the second semiconductor layer. The third semiconductor layer is between the second peripheral circuit and the second bonding interface.

First claim

What is claimed is:

1 . A three-dimensional (3D) memory device, comprising:
a first semiconductor structure comprising:
an array of NAND memory strings; and
a first semiconductor layer in contact with sources of the array of NAND memory strings;
a second semiconductor structure comprising:
a third peripheral circuit of the array of NAND memory strings, the third peripheral circuit comprising a third transistor; and
a second semiconductor layer in contact with the third transistor;
a third semiconductor structure comprising:
a second peripheral circuit of the array of NAND memory strings, the second peripheral circuit comprising a second transistor; and
a third semiconductor layer in contact with the second transistor;
a first bonding interface between the first semiconductor structure and the second semiconductor structure, wherein the third peripheral circuit is between the first bonding interface and the second semiconductor layer; and a second bonding interface between the second semiconductor structure and the third semiconductor structure, wherein the third semiconductor layer is between the second peripheral circuit and the second bonding interface.

2 . The 3D memory device of claim 1 , wherein the first semiconductor layer comprises single crystalline silicon.

3 . The 3D memory device of claim 1 , wherein the first semiconductor layer comprises polysilicon.

4 . The 3D memory device of claim 3 , wherein the second semiconductor structure further comprises a handle substrate on a side of the second semiconductor structure away from the first semiconductor structure.

5 . The 3D memory device of claim 1 , wherein a thickness of the second semiconductor layer is greater than a thickness of the third semiconductor layer.

6 . The 3D memory device of claim 1 , wherein
the third transistor comprises a third gate dielectric; the second transistor comprises a second gate dielectric; and a thickness of the third gate dielectric is greater than a thickness of the second gate dielectric.

7 . The 3D memory device of claim 6 , wherein a difference between the thicknesses of the third and second gate dielectrics is at least 5-fold.

8 . The 3D memory device of claim 6 , wherein
the second semiconductor structure further comprises a fourth peripheral circuit of the array of NAND memory strings, the fourth peripheral circuit comprising a fourth transistor comprising a third gate dielectric; the third semiconductor structure further comprises a first peripheral circuit of the array of NAND memory strings, the first peripheral circuit comprising a first transistor comprising a first gate dielectric; and the first and fourth gate dielectrics have a same thickness.

9 . The 3D memory device of claim 8 , wherein the thickness of the first and fourth gate dielectrics is between the thicknesses of the third and second gate dielectrics.

10 . The 3D memory device of claim 8 , wherein the first and fourth peripheral circuits comprise at least one of a page buffer circuit or a logic circuit.

11 . The 3D memory device of claim 1 , wherein
the second semiconductor structure further comprises a first interconnect layer between the first bonding interface and the third peripheral circuit, the first interconnect layer comprising a first interconnect coupled to the third transistor; and the third semiconductor structure further comprises a second interconnect layer such that the second peripheral circuit is between the second bonding interface and the second interconnect layer, the second interconnect layer comprising a second interconnect coupled to the second transistor.

12 . The 3D memory device of claim 11 , wherein the second interconnect comprises copper, and the first interconnect comprises tungsten.

13 . The 3D memory device of claim 1 , wherein
the second semiconductor structure further comprises a first contact through the second semiconductor layer; and the third semiconductor structure further comprises a second contact through the third semiconductor layer and coupled to the first contact.

14 . The 3D memory device of claim 1 , wherein the third semiconductor structure further comprises a pad-out interconnect layer such that the second peripheral circuit is between the pad-out interconnect layer and the third semiconductor layer.

15 . The 3D memory device of claim 1 , wherein the second peripheral circuit comprises an input/output (I/O) circuit, and the third peripheral circuit comprises a driving circuit.

16 . The 3D memory device of claim 1 , further comprising:
a third voltage source coupled to the third peripheral circuit and configured to provide a third voltage to the first peripheral circuit; and a second voltage source coupled to the second peripheral circuit and configured to provide a second voltage to the second peripheral circuit, wherein the third voltage is greater than the second voltage.

17 . The 3D memory device of claim 1 , wherein
the first semiconductor structure further comprises a first bonding layer at the first bonding interface and comprising a first bonding contact; the second semiconductor structure further comprises a second bonding layer at the first bonding interface and comprising a second bonding contact; and the first bonding contact is in contact with the second bonding contact at the first bonding interface.

18 . The 3D memory device of claim 1 , wherein the array of NAND memory strings is between the first bonding interface and the first semiconductor layer.

19 . A three-dimensional (3D) memory device, comprising:
a first semiconductor structure comprising:
an array of NAND memory strings, and
a first semiconductor layer in contact with ends of the array of NAND memory strings;
a second semiconductor structure comprising:
a third peripheral circuit of the array of NAND memory strings comprising third transistors, and
a second semiconductor layer in contact with the third transistors; and
a third semiconductor structure comprising:
a second peripheral circuit of the array of NAND memory strings comprising second transistors, and
a third semiconductor layer in contact with the second transistors,
wherein the first semiconductor structure, the second semiconductor structure and the third semiconductor structure are stacked in a vertical direction, and the second semiconductor layer and the third semiconductor layer are between the third peripheral circuit and the second peripheral circuit.

20 . The 3D memory device of claim 19 , wherein the second semiconductor layer and the third semiconductor layer are separated from each other by a bonding interface.

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Chen Liang
• Liu Wei
• Wang Yanhong
• Xia Zhiliang
• Zhou Wenxi
• Zhang Kun
• Yang Yuancheng
• Huang Shiqi

Classifications

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W72/90

  Bond pads, in general · CPC title

• H10W80/00

  Direct bonding of chips, wafers or substrates · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/00 Primary

  Package configurations · CPC title