Field effect transistors having different stress control liners and method of making the same

Patent metadata

Field	Value
Publication number	US-10355100-B1
Application number	US-201815982266-A
Country	US
Kind code	B1
Filing date	May 17, 2018
Priority date	May 17, 2018
Publication date	Jul 16, 2019
Grant date	Jul 16, 2019

Abstract

A first field effect transistor and a second field effect transistor are formed on a substrate. A silicon nitride liner is formed over the first field effect transistor and the second field effect transistor. An upper portion of the silicon nitride liner is converted into a thermal silicon oxide liner. A lower portion of the silicon nitride liner remains as a silicon nitride material portion. A first portion of the thermal silicon oxide liner is removed from above the second field effect transistor, and a second portion of the thermal silicon oxide liner remains above the first field effect transistor. Selective presence of the silicon oxide liner provides differential stress within the channels of the first and second field effect transistors, which can be employed to optimize performance of different types of field effect transistors.

First claim

The invention claimed is:

1. A semiconductor structure comprising:
a first field effect transistor and a second field effect transistor located on a substrate;
a silicon nitride liner continuously extending over the first field effect transistor and the second field effect transistor;
a thermal silicon oxide liner extending over the first field effect transistor and not extending over the second field effect transistor; and
a planarization dielectric layer contacting the thermal silicon oxide liner over the first field effect transistor and contacting the silicon nitride liner over the second field effect transistor;
wherein an interface between the silicon nitride liner and the thermal silicon oxide comprises a silicon oxynitride transition layer which has a compositional gradient such that: atomic concentration of nitrogen atoms increases with a nitrogen concentration gradient from a side of the thermal silicon oxide liner to a side of the silicon nitride liner over a distance of at least 0.6 nm; and atomic concentration of oxygen atoms increases with an oxygen concentration gradient from the side of the silicon nitride liner to the side of the thermal silicon oxide liner over the distance of at least 0.6 nm.

2. The semiconductor structure of claim 1 , further comprising a continuous silicon oxide liner continuously extending over the first and second field effect transistors and contacting a bottom surface of the silicon nitride liner, wherein:
atomic concentration of oxygen atoms decreases to substantially zero from a side of the continuous silicon oxide liner to the side of the silicon nitride liner over a distance less than 0.6 nm; and
atomic concentration of nitrogen atoms decreases to substantially zero from the side of the silicon nitride liner to the side of the continuous silicon oxide liner over the distance less than 0.6 nm.

3. The semiconductor structure of claim 1 , wherein:
the semiconductor structure comprises a CMOS device,
the silicon nitride liner generates tensile stress in respective underlying structures;
the thermal silicon oxide liner generates compressive stress in respective underlying structures;
the first field effect transistor comprises a p-type field effect transistor; and
the second field effect transistor comprises an n-type field effect transistor.

4. The semiconductor structure of claim 1 , wherein the first field effect transistor and the second field effect transistor include channels having a same type of doping.

5. The semiconductor structure of claim 4 , wherein the first field effect transistor comprises a lower voltage field effect transistor than the second field effect transistor.

6. The semiconductor structure of claim 1 , further comprising a third field effect transistor located on the substrate.

7. The semiconductor structure of claim 6 , wherein:
horizontal portions of the silicon nitride liner have a uniform silicon nitride thickness throughout;
the thermal silicon oxide liner has a first silicon oxide thickness over the first field effect transistor;
the thermal silicon oxide liner extends over the third field effect transistor with a second silicon oxide thickness that is less than the first silicon oxide thickness; and
a ratio of the first silicon oxide thickness to the uniform silicon nitride thickness is in a range from 0.1 to 10.

8. The semiconductor structure of claim 1 , wherein horizontal portions of the thermal silicon oxide liner overlying active regions of the first field effect transistor have a same thickness as tapered portions of the thermal silicon oxide liner overlying a gate spacer of the first field effect transistor and a horizontal portion of the thermal silicon oxide liner overlying a gate electrode of the first field effect transistor.

9. A three-dimensional NAND memory device, comprising:
the semiconductor structure of claim 1 located over a substrate;
an alternating stack of insulating layers and word lines located over the semiconductor structure; and
memory stack structures extending through the alternating stack and comprising a respective memory film and a vertical semiconductor channel.

Assignees

• Sandisk Technologies Llc

Inventors

• Ueda Yu
• Obu Tomoyuki
• Yoshizawa Kazutaka
• Aoki Yasuyuki
• Takii Eisuke
• Nishida Akio

Classifications

• H10P50/283

  by chemical means · CPC title

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title

• H10P14/6927

  the material being a silicon oxynitride, e.g. SiON or SiON:H · CPC title

• H10P14/6529

  by exposure to a gas or vapour · CPC title