Host-based and client-based command scheduling in large bandwidth memory systems

Patent metadata

Field	Value
Publication number	US-12524153-B2
Application number	US-202017133987-A
Country	US
Kind code	B2
Filing date	Dec 24, 2020
Priority date	Sep 14, 2017
Publication date	Jan 13, 2026
Grant date	Jan 13, 2026

Abstract

A high-bandwidth memory (HBM) system includes an HBM device and a logic circuit. The logic circuit receives a first command from the host device and converts the received first command to a processing-in-memory (PIM) command that is sent to the HBM device through the second interface. A time between when the first command is received from the host device and when the HBM system is ready to receive another command from the host device is deterministic. The logic circuit further receives a fourth command and a fifth command from the host device. The fifth command requests time-estimate information relating to a time between when the fifth command is received and when the HBM system is ready to receive another command from the host device. The time-estimate information includes a deterministic period of time and an estimated period of time for a non-deterministic period of time.

First claim

What is claimed is:

1 . A memory system, comprising:
a memory device including processing-in-memory (PIM); and a logic circuit comprising a first interface capable of being coupled to a host device using a first bus and a second bus and a second interface coupled to the memory device using a third bus, the logic circuit capable of receiving a first command from the host device using the first interface via the first bus, the logic circuit receiving, based on the first command, a second command for a PIM operation, the second command being sent from the host device using the second bus, the logic circuit sending, using the third bus, a third command for the PIM operation when the PIM operation is being performed using the third bus, wherein the third command is based on a timing of an action performed on result of the PIM operation, and wherein the third bus is internal to the memory device.

2 . The memory system of claim 1 , wherein the first command from the host device is for the PIM operation on a first address in the memory device or a first address and a second address in a row in the memory device.

3 . The memory system of claim 2 , wherein the first command from the host device is for the PIM operation within one or more banks in a channel in the memory device.

4 . The memory system of claim 1 , wherein the first command from the host device is for the PIM operation in a first bank and a second bank in the memory device.

5 . The memory system of claim 1 , wherein:
the first interface comprises a command and address (CA) bus and a data bus; the first command from the host device comprises a first host command received from the host device using the data bus of the first interface; the logic circuit is capable of receiving a second host command from the host device using the CA bus of the first interface; and the logic circuit further receives a third host command from the host device using the CA bus and a fourth host command using the data bus for a second PIM operation in the memory device, the fourth host command requesting an estimate information relating to a latency for the fourth host command being received from the host device and the memory system being ready to receive another command from the host device, the estimate information including a deterministic portion and an estimated portion.

6 . The memory system of claim 1 , wherein:
the first interface comprises a command and address (CA) bus and a data bus; the first command from the host device comprises a first host command received from the host device using the data bus of the first interface; the logic circuit is capable of receiving a second host command from the host device using the CA bus of the first interface; and the logic circuit further receives a third host command from the host device using the CA bus and a fourth host command using the data bus for a second PIM operation in the memory device, the fourth host command requesting an estimate information relating to a latency for the fourth host command being received from the host device and the memory system being ready to receive another command from the host device, the estimate information including a deterministic portion and a credit-based portion.

7 . The memory system of claim 1 , wherein:
the first interface comprises a command and address (CA) bus and a data bus; the first command from the host device comprises a first host command received from the host device using the data bus of the first interface; the logic circuit is capable of receiving a second host command from the host device using the CA bus of the first interface; and the logic circuit further receives a third host command from the host device using the CA bus and a fourth host command using the data bus for a second PIM operation in the memory device, the fourth host command requesting an estimate information relating to a latency for the fourth host command being received from the host device and the memory system being ready to receive another command from the host device, the estimate information including a deterministic portion and a retry portion.

8 . The memory system of claim 1 , wherein a latency for the memory system receiving the first command from the host device and being ready to receive another command from the host device is deterministic.

9 . A memory system, comprising:
a memory device; and a logic circuit comprising a first interface capable of being coupled to a host device using a first bus and a second bus and a second interface coupled to the memory device using a third bus, the logic circuit capable of receiving a first command from the host device via the first bus and receiving, based on the first command, using the second interface, a second command from the host device for a processing-in-memory (PIM) operation using the third bus to the memory device, the logic circuit further capable of sending, to the host device, scheduling information for the PIM operation using the second bus, wherein the scheduling information includes an indication of completion of the PIM operation, and wherein the third bus is internal to the memory device.

10 . The memory system of claim 9 , wherein the first command comprises a first host command, the logic circuit is further capable of receiving a second host command from the host device, the second host command requesting a first estimate information, based on the second command being received from the host device, for the memory system being ready to receive another command from the host device, the first estimate information including a non-deterministic portion.

11 . The memory system of claim 10 , wherein the non-deterministic portion comprises an estimated latency.

12 . The memory system of claim 10 , wherein the PIM operation is a first PIM operation, the logic circuit further receives a third host command from the host device for a second PIM operation in the memory device, and a fourth host command from the host device, the fourth host command requesting a second estimate information, based on the third host command being received from the host device, for the memory system being ready to receive another command from the host device, the second estimate information including a deterministic portion and a credit-based portion.

13 . The memory system of claim 12 , wherein the deterministic portion is a first deterministic portion, and wherein the logic circuit further receives a fifth host command from the host device for a third PIM operation in the memory device, and a sixth host command from the host device, the sixth host command requesting a third estimate information, based on the sixth host command being received from the host device, for the memory system being ready to receive another command from the host device, the third estimate information including a second deterministic portion and a retry portion.

14 . The memory system of claim 13 , wherein the logic circuit further receives a seventh host command from the host device for a fourth PIM operation in the memory device, a first latency, based on the seventh host command being received from the host device, for the memory system being ready to receive another command from the host device being deterministic.

15 . The memory system of claim 14 , wherein the seventh host command is for the fourth PIM operation on a first address in the memory device or the first address and a second address in a row in the memory device.

16 . The memory system of claim 15 , wherein the logic circuit further receives an eighth host command

Assignees

• Samsung Electronics Co Ltd

Inventors

• Malladi Krishna T
• Zheng Hongzhong
• Brennan Robert

Classifications

• G06F13/4243

  with synchronous protocol · CPC title

• G06F13/1615

  using a concurrent pipeline structrure · CPC title

• G06F15/7821

  Tightly coupled to memory, e.g. computational memory, smart memory, processor in memory · CPC title

• G06F12/02

  Addressing or allocation; Relocation (program address sequencing G06F9/00; arrangements for selecting an address in a digital store G11C8/00) · CPC title

• G06F13/1689 Primary

  Synchronisation and timing concerns (synchronisation on a memory bus G06F13/4234) · CPC title