System and method for reducing command scheduling constraints of memory circuits

Patent metadata

Field	Value
Publication number	US-9542353-B2
Application number	US-92922507-A
Country	US
Kind code	B2
Filing date	Oct 30, 2007
Priority date	Feb 9, 2006
Publication date	Jan 10, 2017
Grant date	Jan 10, 2017

Abstract

A memory circuit system and method are provided. An interface circuit is capable of communication with a plurality of memory circuits and a system. In use, the interface circuit is operable to interface the memory circuits and the system for reducing command scheduling constraints of the memory circuits.

First claim

What is claimed is:

1. A sub-system, comprising:
a first number of physical memory circuits limited by one or more device command scheduling constraints;
an interface circuit electrically connected to the physical memory circuits via multiple independent data paths and electrically coupled to a memory controller via a separate data path, the interface circuit configured to:
communicate with the first number of physical memory circuits and the memory controller,
interface the first number of physical memory circuits to simulate a different, second number of virtual memory circuits,
present the different, second number of virtual memory circuits to the memory controller,
translate row-activation commands or column-access commands, received from the memory controller directed to at least one of the different, second number of virtual memory circuits, to corresponding row-activation commands or column-access commands,
issue the corresponding row-activation commands or column-access commands to at least one of the first number of physical memory circuits,
combine data received on the data paths from any of the first number of physical memory circuits, and
provide the combined data to the memory controller, such that the different, second number of virtual memory circuits appear to the memory controller as free from the one or more device command scheduling constraints;

wherein each of the first number of physical memory circuits comprises a respective plurality of physical memory banks, and
wherein, for each of the second number of virtual memory circuits, the interface circuit is configured to simulate a respective plurality of virtual memory banks using two or more physical memory banks of at least two physical memory circuits of the first number of physical memory circuits.

2. The sub-system as set forth in claim 1 , wherein the device command scheduling constraints include one or more inter-device command scheduling constraints.

3. The sub-system as set forth in claim 2 , wherein the one or more inter-device command scheduling constraints include at least one of a rank-to-rank data bus turnaround time or an on-die termination (ODT) control switching time.

4. The sub-system as set forth in claim 1 , wherein the device command scheduling constraints include at least one of a column-to-column delay time (tCCD), a row-to-row activation delay time (tRRD), a four-bank activation window time (tFAW), or a write-to-read turn-around time (tWTR).

5. The sub-system as set forth in claim 1 , wherein the interface circuit is further configured to issue row-access commands and column-access commands.

6. The sub-system as set forth in claim 1 , wherein the interface circuit is further configured to issue commands to different memory circuits of the first number of physical memory circuits using separate busses.

7. The sub-system as set forth in claim 1 , wherein the interface circuit includes a circuit that is positioned on a dual in-line memory module (DIMM).

8. The sub-system as set forth in claim 1 , wherein the interface circuit is a buffer, a register, or an advanced memory buffer (AMB).

9. The sub-system as set forth in claim 1 , wherein the interface circuit and the first number of physical memory circuits form a stack.

10. The sub-system as set forth in claim 1 , wherein the first number of physical memory circuits include a plurality of dynamic random access memory (DRAM) circuits.

11. A method, comprising:
interfacing a first number of physical memory circuits limited by one or more intra-device command scheduling constraints, in order to simulate a different, second number of virtual memory circuits;
presenting the different, second number of virtual memory circuits to a memory controller;
translating row-activation commands or column-access commands received from the memory controller directed to at least one of the different, second number of virtual memory circuits to corresponding row-activation commands or column-access commands;
issuing the corresponding row-activation commands or column-access commands to at least one of the first number of physical memory circuits;
combining data received on data paths from any of the first number of physical memory circuits; and
providing the combined data to the memory controller, such that the different, second number of virtual memory circuits appear to the memory controller as free from the one or more device command scheduling constraints,
wherein each of the first number of physical memory circuits comprises a respective plurality of physical memory banks, and
wherein, for each of the second number of virtual memory circuits, an interface circuit is configured to simulate a respective plurality of virtual memory banks using two or more physical memory banks of at least two physical memory circuits of the first number of physical memory circuits.

12. A system, comprising:
a host system;
a first number of physical memory circuits limited by one or more device command scheduling constraints;
an interface circuit electrically connected to the physical memory circuits via multiple independent data paths and electrically coupled to the host system via a separate data path, the interface circuit configured to:
communicate with the first number of physical memory circuits and the host system,
interface the first number of physical memory circuits-to simulate a different, second number of virtual memory circuits,
present the different, second number of virtual memory circuits to the host system,
translate row-activation commands or column-access commands, received from the host system directed to at least one of the different, second number of virtual memory circuits, to corresponding row-activation commands or column-access commands,
issue the corresponding row-activation commands or column-access commands to at least one of the first number of physical memory circuits,
combine data received on the data paths from any of the first number of physical memory circuits, and
provide the combined data to the host system, such that the different, second number of virtual memory circuits appear to the host system as free from the one or more device command scheduling constraints;
wherein each of the first number of physical memory circuits comprises a respective plurality of physical memory banks, and
wherein, for each of the second number of virtual memory circuits, the interface circuit is configured to simulate a respective plurality of virtual memory banks using two or more physical memory banks of at least two physical memory circuits of the first number of physical memory circuits.

13. The system as set forth in claim 12 , wherein the first number of physical memory circuits and the interface circuit are positioned on a dual in-line memory module (DIMM).

14. The system as set forth in claim 12 , wherein the first number of physical memory circuits and the interface circuit are positioned on a memory module that is configured to use a bus to communicate with a processor.

Assignees

• Rajan Suresh Natarajan
• Schakel Keith R
• Smith Michael John Sebastian
• Wang David T
• Weber Frederick Daniel
• Google Inc

Inventors

• Rajan Suresh Natarajan
• Schakel Keith R
• Smith Michael John Sebastian
• Wang David T
• Weber Frederick Daniel

Classifications

• G11C11/406

  Management or control of the refreshing or charge-regeneration cycles · CPC title

• G06F13/28

  using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) · CPC title

• G11C11/4093

  Input/output [I/O] data interface arrangements, e.g. data buffers · CPC title

• Y02B60/1235

  Cross-Sectional Technologies · mapped topic

• Y02B60/1228

  Cross-Sectional Technologies · mapped topic