Multi-channel testing

Patent metadata

Field	Value
Publication number	US-9633748-B2
Application number	US-201514828144-A
Country	US
Kind code	B2
Filing date	Aug 17, 2015
Priority date	Aug 17, 2015
Publication date	Apr 25, 2017
Grant date	Apr 25, 2017

Abstract

Apparatus and methods can include an interface chip that can include a test channel to couple to a memory tester, a memory channel controller to couple with a plurality of memory arrays via a plurality of memory channels, and a test circuit coupled between the test channel and the channel controller, the test circuit to provide first and second test clock information to the memory channel controller. In certain examples, the test circuit can operate to receive multiple commands and to propagate the multiple commands to groups of memory channels substantially simultaneously in order to test cross-channel interference using the multi-channel memory. Additional apparatus and methods are disclosed.

First claim

What is claimed is:

1. An apparatus comprising:
a test channel to couple to a memory tester;
a memory channel controller to couple with a plurality of memory arrays via a plurality of memory channels;
a test circuit coupled between the test channel and the memory channel controller, the test circuit to provide first and second test clock information to the memory channel controller;
wherein the test circuit is to receive a first command in synchronization with the first test clock information, to delay propagation of the first command to a first one or more memory channels of the plurality of memory channels using the second test clock information, to receive a second command from the test circuit, after reception of the first command, in synchronization with the first test clock information, and to propagate the second command to a second one or more memory channels of the plurality of memory channels in synchronization with the first test clock information; and
wherein the propagation of the first command to the first one or more of the memory channels and the propagation of the second command to the second one or more memory channels is to at least partially overlap in time.

2. The apparatus of claim 1 , wherein the first command is different than the second command.

3. The apparatus of claim 1 , wherein the first test clock information includes a frequency different than the second test clock information.

4. The apparatus of claim 1 , wherein a phase of the first test clock information is different than a phase of the second test clock information.

5. The apparatus of claim 1 , wherein a test includes the propagation of the first command and the second command using the first one or more memory channels and the second one or more memory channels; and
wherein a plurality of tests includes a different phase of the second test clock information for each test of the plurality of tests.

6. The apparatus of claim 1 , wherein the test circuit is to receive the second test clock information at an input.

7. The apparatus of claim 1 , wherein the test circuit includes a phase-lock loop (PLL) to generate the second test clock information.

8. The apparatus of claim 1 , including a divider circuit to receive clock information from the memory tester and to generate the first test clock information and the second test clock information.

9. The apparatus of claim 1 , including a multi-channel bus to couple an electronic device processor with the memory channel controller.

10. The apparatus of claim 1 , including a first-in, first-out circuit (FIFO) to receive the first command on a transition of the first test clock information and to subsequently output the first command on a transition of the second test clock information.

11. The apparatus of claim 10 , including one or more delay circuits to receive the first command from the FIFO, to receive the second test clock information and to delay the propagation of the first command to the memory channel controller using the one or more delay circuits and the second test clock information.

12. The apparatus of claim 1 , wherein the memory channel controller includes a selection circuit to receive a selection command and to select the first one or more memory channels from the plurality of memory channels based on the selection command.

13. The apparatus of claim 1 , including a built-in self-test (BIST) circuit to provide the first and second commands and test data associated the first and second commands.

14. The apparatus of claim 13 , wherein the BIST is configured to receive actual data from the plurality of memory channels in response to the first and second commands and the test data, and to provide an indication of performance of the plurality of memory arrays with respect to the propagation of the first commands to the first one or more of the memory channels and the propagation of the second command to the second one or more memory channels; and
wherein the indication includes Shmoo plot information.

15. The apparatus of claim 14 , wherein variable data of the Shmoo plot information includes one of the first command, the second command, or a phase of the second test clock information.

16. A method comprising:
receiving, in synchronization with first test clock information, a first test command at a test circuit coupled to memory via a plurality of memory channels;
delaying propagation of the first command to a first one or more memory channels of the plurality of memory channels using second test clock information;
receiving, after reception of the first command and in synchronization with the first test clock, a second command at the test circuit; and
propagating the second command to a second one or more memory channels of the plurality of memory channels in synchronization with the first test clock information; wherein the delaying propagation of the first command to the first one or more memory channels and the propagating of the second command to the second one or more memory channels includes receiving at least a portion of the first command at the first one or more memory channels simultaneous with receiving the second command at the second one or more memory channels.

17. The method of claim 16 , wherein the first command is different than the second command.

18. The method of claim 16 , wherein the first test clock information includes a frequency different than a frequency of the second test clock information.

19. The method of claim 16 , wherein a phase of the first test clock information is different than a phase of the second test clock information.

20. The method of claim 16 , wherein conducting a test cycle includes propagating the first command and the second command partially simultaneously using the first one or more memory channels and the second one or more memory channels; and
wherein the method includes conducting a plurality of tests, wherein each test of the plurality of tests includes using a different phase of the second test clock information.

21. A memory interface chip comprising:
a multiple channel bus to couple to a processor;
a multiple channel memory bus to couple to a plurality of memory arrays;
a channel controller to couple the multiple channel bus with the multiple channel memory bus;
a test circuit coupled to the channel controller, the test circuit configured to substantially simultaneously propagate first test command information via a first one or more channels of the multiple channel memory bus and second test command information via a second one or more channels of the multiple channel memory bus to identify communication issues during simultaneous use of channels of the multiple channel memory bus; and
wherein the memory interface chip is configured to delay propagation of the first command information to the first one or more channels of the multiple channel memory bus using first test clock information, and, after initiating propagation of the first command information, to propagate the second command to the second one or more channels of the multiple channel memory bus in synchronization with second test clock information.

22. The memory interface chip of claim 21 , wherein the interface chip is to receive the first test clock information at a first input.

23. The memory interface chip of claim 21 , including a phase-lock loop to generate the first test clock information.

24. The memory interface chip of claim 21 , wherein the interfa

Assignees

• Micron Technology Inc

Inventors

• Shibata Tomoyuki

Classifications

• G11C29/56012 Primary

  Timing aspects, clock generation, synchronisation · CPC title

• G11C29/38 Primary

  Response verification devices · CPC title

• G11C29/12015

  comprising clock generation or timing circuitry · CPC title

• G11C29/36

  Data generation devices, e.g. data inverters · CPC title

• G11C2029/5602

  Interface to device under test · CPC title