Memory device and memory system including the memory device

Patent metadata

Field	Value
Publication number	US-2016155490-A1
Application number	US-201514696030-A
Country	US
Kind code	A1
Filing date	Apr 24, 2015
Priority date	Nov 27, 2014
Publication date	Jun 2, 2016
Grant date	—

Abstract

A memory device includes a first memory bank comprising first and second memory blocks; a second memory bank comprising third and fourth memory blocks; and a bank selection unit suitable for selecting a memory bank corresponding to a bank address among the first and the second memory banks when an active command is applied, wherein the selected memory bank performs row access on a word line of an unselected memory block, while activating a word line of a memory block that is selected by a block address among memory blocks of the selected memory bank.

First claim

What is claimed is:

1 . A memory device, comprising:
a first memory bank comprising first and second memory blocks; a second memory bank comprising third and fourth memory blocks; and a bank selection unit suitable for selecting a memory bank corresponding to a bank address among the first and the second memory banks when an active command is applied, wherein the selected memory bank performs row access on a word line of an unselected memory block, while activating a word line of a memory block that is selected by a block address among memory blocks of the selected memory bank.

2 . The memory device of claim 1 , wherein the row access on the word line comprises one or more of an operation for activating the word line, an operation for performing normal refresh on the word line, and an operation for performing target refresh on the word line.

3 . The memory device of claim 2 , wherein the selected memory bank activates a word line that corresponds to a row address among word lines of the selected memory block and a word line that corresponds to the row address among word lines of the unselected memory block, together.

4 . The memory device of claim 3 , wherein the selected memory bank performs column access on memory cells connected to the activated word line of the selected memory block, and memory cells connected to the activated word line of the unselected memory block, and
wherein the column access on the memory cells comprises an operation for writing data in the memory cells and an operation for reading data from the memory cells.

5 . The memory device of claim 4 , wherein the selected memory bank performs the column access on the selected memory block and the unselected memory block at an interval of column address strobe to column address strobe delay (tCCD).

6 . The memory device of claim 3 , wherein when a precharge command is applied, the selected memory bank precharges the activated word line of the selected memory block and the activated word line of the unselected memory block.

7 . The memory device of claim 2 , further comprising:
an address counting unit suitable for generating a counting address by performing a counting operation, wherein the selected memory bank refreshes a word line that corresponds to the counting address among word lines of the unselected memory block while activating a word line that corresponds to a row address among word lines of the selected memory block.

8 . The memory device of claim 2 , further comprising:
an address storage unit suitable for storing an address of a word line having an active number equal to or greater than a reference number, an active frequency equal to or higher than a reference frequency, or an active time equal to or longer than a reference time, wherein the selected memory bank refreshes a word line that is adjacent to the word line corresponding to the address of the address storage unit among word lines of the unselected memory block while activating a word line that corresponds to a row address among word lines of the selected memory block.

9 . The memory device of claim 2 , further comprising:
an address counting unit suitable for generating a counting address by performing a counting operation; and an address storage unit suitable for storing an address of a word line having an active number equal to or greater than a reference number, an active frequency equal to or higher than a reference frequency, or an active time equal to or longer than a reference time.

10 . The memory device of claim 9 , wherein, while activating a word line that corresponds to a row address among word lines of the selected memory block, the selected memory bank:
activates a word line that corresponds to the row address among word lines of the unselected memory block if the selected memory bank is set in a first mode; refreshes a word line that corresponds to the counting address among the word lines of the unselected memory block if the selected memory bank is set in a second mode; and refreshes a word line that is adjacent to the word line corresponding to the address of the address storage unit among the word lines of the unselected memory block if the selected memory bank is set in a third mode.

11 . The memory device of claim 2 , further comprising:
a first bank control unit suitable for generating first and second block control signals corresponding to the first and the second memory blocks, respectively, and activating the first and the second block control signals together when the first memory bank is selected; a second bank control unit suitable for generating third and fourth block control signals corresponding to the third and the fourth memory blocks, respectively, and activating the third and the fourth block control signals together when the second memory bank is selected; and a global bus suitable for transferring data of the selected memory bank.

12 . The memory device of claim 11 , wherein the first memory bank comprises:
a first block control unit suitable for controlling the row access to the first memory block in response to the first block control signal; a second block control unit suitable for controlling the row access to the second memory block in response to the second block control signal; a first local bus suitable for transferring data between the first memory block and the global bus; a second local bus suitable for transferring data between the second memory block and the global bus; and wherein the second memory bank comprises: a third block control unit suitable for controlling the row access to the third memory block in response to the third block control signal; a fourth block control unit suitable for controlling the row access to the fourth memory block in response to the fourth block control signal; a third local bus suitable for transferring data between the third memory block and the global bus; and a fourth local bus suitable for transferring data between the fourth memory block and the global bus.

13 . A memory device, comprising:
a first memory bank comprising first and second memory blocks; a second memory bank comprising third and fourth memory blocks; and a bank selection unit suitable for selecting a memory bank corresponding to a bank address among the first and the second memory banks when an active command is applied, wherein in a single mode, the selected memory bank activates a word line of a memory block that is selected by a block address among memory blocks of the selected memory bank, and in a dual mode, the selected memory bank performs row access on a word line of an unselected memory block other than the selected memory block while activating the word line of the selected memory block.

14 . The memory device of claim 13 , wherein the row access on the word line comprises one or more of an operation for activating the word line, an operation for performing normal refresh on the word line, and an operation for performing target refresh on the word line.

15 . The memory device of claim 14 , wherein in the dual mode, the selected memory bank activates a word line that corresponds to a row address among word lines of the selected memory block and a word line that corresponds to the row address among word lines of the unselected memory block together.

16 . The memory device of claim 14 , further comprising:
an address counting unit suitable for generating a counting address by performing a counting operation, wherein in the dual mode, the selected memory bank refreshes a word line that corresponds to the counting address among

Assignees

• Sk Hynix Inc

Inventors

• Shin Sun-Hye
• Park Nak-Kyu

Classifications

• G11C11/4085 Primary

  Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge · CPC title

• G11C11/406

  Management or control of the refreshing or charge-regeneration cycles · CPC title

• G11C11/4096

  Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches · CPC title

• G11C11/4063

  Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing · CPC title

• G11C11/40603

  Arbitration, priority and concurrent access to memory cells for read/write or refresh operations · CPC title