Semiconductor device having a necked semiconductor body and method of forming semiconductor bodies of varying width

Patent metadata

Field	Value
Publication number	US-12520519-B2
Application number	US-202418608294-A
Country	US
Kind code	B2
Filing date	Mar 18, 2024
Priority date	Dec 22, 2011
Publication date	Jan 6, 2026
Grant date	Jan 6, 2026

Abstract

Semiconductor devices having necked semiconductor bodies and methods of forming semiconductor bodies of varying width are described. For example, a semiconductor device includes a semiconductor body disposed above a substrate. A gate electrode stack is disposed over a portion of the semiconductor body to define a channel region in the semiconductor body under the gate electrode stack. Source and drain regions are defined in the semiconductor body on either side of the gate electrode stack. Sidewall spacers are disposed adjacent to the gate electrode stack and over only a portion of the source and drain regions. The portion of the source and drain regions under the sidewall spacers has a height and a width greater than a height and a width of the channel region of the semiconductor body.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a semiconductor body; a gate electrode stack over a portion of the semiconductor body to define a channel region in the semiconductor body under the gate electrode stack, a first source or drain region in the semiconductor body at a first side of the gate electrode stack, and a second source or drain region in the semiconductor body at a second side of the gate electrode stack, the second side opposite the first side; a first sidewall spacer adjacent to the first side of the gate electrode stack and over the first source or drain region, the first source or drain region having a width adjacent to the channel region and beneath the first sidewall spacer, the width greater than a first width of the channel region of the semiconductor body and greater than a second width of the semiconductor body, wherein the width of the first source or drain region is approximately 6-40% greater than first the width of the channel region, and wherein the second width of the channel region is parallel with and different than the first width of the channel region; and a second sidewall spacer adjacent to the second side of the gate electrode stack and over the second source or drain region.

2 . The semiconductor device of claim 1 , wherein the width of the first source or drain region is approximately 2-4 nanometers greater than the width of the channel region.

3 . The semiconductor device of claim 1 , wherein the width of the channel region is in a center of the channel region.

4 . The semiconductor device of claim 1 , wherein the second source or drain region has a width adjacent to the channel region and beneath the second sidewall spacer, the width greater than the width of the channel region of the semiconductor body.

5 . The semiconductor device of claim 1 , wherein the semiconductor body has a width under a bottom of the gate electrode stack that is greater than a width of the semiconductor body at a location adjacent to the gate electrode stack.

6 . A method of fabricating a semiconductor device, the method comprising:
forming a semiconductor body; forming a gate electrode stack over a portion of the semiconductor body to define a channel region in the semiconductor body under the gate electrode stack, a first source or drain region in the semiconductor body at a first side of the gate electrode stack, and a second source or drain region in the semiconductor body at a second side of the gate electrode stack, the second side opposite the first side; forming a first sidewall spacer adjacent to the first side of the gate electrode stack and over the first source or drain region, the first source or drain region having a width adjacent to the channel region and beneath the first sidewall spacer, the width greater than a first width of the channel region of the semiconductor body and greater than a second width of the semiconductor body, wherein the width of the first source or drain region is approximately 6-40% greater than the first width of the channel region, and wherein the second width of the channel region is parallel with and different than the first width of the channel region; and forming a second sidewall spacer adjacent to the second side of the gate electrode stack and over the second source or drain region.

7 . The method of claim 6 , wherein the width of the first source or drain region is approximately 2-4 nanometers greater than the width of the channel region.

8 . The method of claim 6 , wherein the width of the channel region is in a center of the channel region.

9 . The method of claim 6 , wherein the second source or drain region has a width adjacent to the channel region and beneath the second sidewall spacer, the width greater than the width of the channel region of the semiconductor body.

10 . The method of claim 6 , wherein the semiconductor body has a width under a bottom of the gate electrode stack that is greater than a width of the semiconductor body at a location adjacent to the gate electrode stack.

11 . A computing device, comprising:
a board; and a component coupled to the board, the component including an integrated circuit structure, comprising:
a semiconductor body;
a gate electrode stack over a portion of the semiconductor body to define a channel region in the semiconductor body under the gate electrode stack, a first source or drain region in the semiconductor body at a first side of the gate electrode stack, and a second source or drain region in the semiconductor body at a second side of the gate electrode stack, the second side opposite the first side;
a first sidewall spacer adjacent to the first side of the gate electrode stack and over the first source or drain region, the first source or drain region having a width adjacent to the channel region and beneath the first sidewall spacer, the width greater than a first width of the channel region of the semiconductor body and greater than a second width of the semiconductor body, wherein the width of the first source or drain region is approximately 6-40% greater than the first width of the channel region, and wherein the second width of the channel region is parallel with and different than the first width of the channel region; and
a second sidewall spacer adjacent to the second side of the gate electrode stack and over the second source or drain region.

12 . The computing device of claim 11 , wherein the width of the first source or drain region of the integrated circuit structure is approximately 2-4 nanometers greater than the width of the channel region.

13 . The computing device of claim 11 , wherein the width of the channel region of the integrated circuit structure is in a center of the channel region.

14 . The computing device of claim 11 , further comprising:
a memory coupled to the board.

15 . The computing device of claim 11 , further comprising:
a communication chip coupled to the board.

16 . The computing device of claim 11 , further comprising:
a battery coupled to the board.

17 . The computing device of claim 11 , further comprising:
a camera coupled to the board.

18 . The computing device of claim 11 , further comprising:
a display coupled to the board.

19 . The computing device of claim 11 , wherein the component is a packaged integrated circuit die.

20 . The computing device of claim 11 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.

Assignees

• Intel Corp

Inventors

• Sell Bernhard

Classifications

• H10P50/693

  characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane · CPC title

• H10P50/642

  Chemical etching · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10D86/215

  comprising FinFETs · CPC title

• H10D84/853

  comprising FinFETs · CPC title