Semiconductor device having a necked semiconductor body and method of forming semiconductor bodies of varying width

Patent metadata

Field	Value
Publication number	US-10319843-B2
Application number	US-201615275072-A
Country	US
Kind code	B2
Filing date	Sep 23, 2016
Priority date	Dec 22, 2011
Publication date	Jun 11, 2019
Grant date	Jun 11, 2019

Abstract

Semiconductor devices having necked semiconductor bodies and methods of forming semiconductor bodies of varying width are described. For example, a semiconductor device includes a semiconductor body disposed above a substrate. A gate electrode stack is disposed over a portion of the semiconductor body to define a channel region in the semiconductor body under the gate electrode stack. Source and drain regions are defined in the semiconductor body on either side of the gate electrode stack. Sidewall spacers are disposed adjacent to the gate electrode stack and over only a portion of the source and drain regions. The portion of the source and drain regions under the sidewall spacers has a height and a width greater than a height and a width of the channel region of the semiconductor body.

First claim

What is claimed is:

1. A semiconductor structure, comprising:
a silicon body protruding from and continuous with an underlying bulk silicon substrate;
a gate electrode on a gate dielectric on a top and sidewalls of a portion of the silicon body defining a channel region in the silicon body beneath the gate electrode, the gate electrode having a first side and a second side opposite the first side, wherein the channel region comprises first and second tapered portions from a plan view perspective, the first tapered portion widening from a center of the channel region to a first end of the channel region, and the second tapered portion widening from the center of the channel region to a second end of the channel region;
a first source/drain region coupled to the first end of the channel region and adjacent to the first side of the gate electrode;
a second source/drain region coupled to the second end of the channel region and adjacent to the second side of the gate electrode;
a first dielectric sidewall spacer adjacent to the first side of the gate electrode and over only a portion of the first source/drain region; and
a second dielectric sidewall spacer adjacent to the second side of the gate electrode and over only a portion of the second source/drain region.

2. The semiconductor structure of claim 1 , wherein the portion of the first source/drain region under the first dielectric sidewall spacer has a widest width greater than a widest width of the channel region of the silicon body from the plan view perspective, and wherein the portion of the second source/drain region under the second dielectric sidewall spacer has a widest width greater than the widest width of the channel region of the silicon body from the plan view perspective.

3. The semiconductor structure of claim 2 , wherein a portion of the first source/drain region outside the first dielectric sidewall spacer has a widest width greater than the widest width of the portion of the first source/drain region under the first dielectric sidewall spacer from the plan view perspective, and a portion of the second source/drain region outside the second dielectric sidewall spacer has a widest width greater than the widest width of the portion of the second source/drain region under the second dielectric sidewall spacer from the plan view perspective.

4. The semiconductor structure of claim 2 , wherein a portion of the first source/drain region outside the first dielectric sidewall spacer has a widest width approximately the same as the widest width of the portion of the first source/drain region under the first dielectric sidewall spacer from the plan view perspective, and a portion of the second source/drain region outside the second dielectric sidewall spacer has a widest width approximately the same as the widest width of the portion of the second source/drain region under the second dielectric sidewall spacer from the plan view perspective.

5. The semiconductor structure of claim 1 , wherein at least part of the portion of the first source/drain region under the first dielectric sidewall spacer comprises a semiconductor material different than the channel region of the silicon body, and wherein at least part of the portion of the second source/drain region under the second dielectric sidewall spacer comprises the semiconductor material.

6. The semiconductor structure of claim 5 , wherein all of the portion of the first source/drain region under the first dielectric sidewall spacer comprises the semiconductor material, and wherein all of the portion of the second source/drain region under the second dielectric sidewall spacer comprises the semiconductor material.

7. The semiconductor structure of claim 1 , wherein a portion of the first source/drain region outside the first dielectric sidewall spacer comprises a semiconductor material different than the channel region of the silicon body but the portion of the first source/drain region under the first dielectric sidewall spacer does not comprise the semiconductor material, and wherein a portion of the second source/drain region outside the second dielectric sidewall spacer comprises the semiconductor material but the portion of the second source/drain region under the second dielectric sidewall spacer does not comprise the semiconductor material.

8. The semiconductor structure of claim 1 , wherein the channel region has a height approximately 1-2 nanometers less than a height of the portion of the first source/drain region under the first dielectric sidewall spacer and of the portion of the second source/drain region under the second dielectric sidewall spacer.

9. The semiconductor structure of claim 1 , wherein the portion of the first source/drain region under the first dielectric sidewall spacer and the portion of the second source/drain region under the second dielectric sidewall spacer have a height approximately 1-7% greater than a height of the channel region, and have a width approximately 6-40% greater than a width of the channel region.

10. The semiconductor structure of claim 1 , wherein the gate dielectric comprises a top high-k portion and a bottom silicon dioxide or silicon oxy-nitride portion.

11. The semiconductor structure of claim 10 , wherein the gate electrode comprises a metal workfunction-setting layer.

12. The semiconductor structure of claim 11 , wherein the gate electrode further comprises a non-work-function-setting fill material above the metal workfunction-setting layer.

Assignees

• Intel Corp

Inventors

• Sell Bernhard

Classifications

• H10P50/693

  characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane · CPC title

• H10P50/642

  Chemical etching · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H01L21/823412

  Electricity · mapped topic

• H01L29/41791

  Electricity · mapped topic