Semiconductor device having a necked semiconductor body and method of forming semiconductor bodies of varying width

Patent metadata

Field	Value
Publication number	US-9711410-B2
Application number	US-201414569166-A
Country	US
Kind code	B2
Filing date	Dec 12, 2014
Priority date	Dec 22, 2011
Publication date	Jul 18, 2017
Grant date	Jul 18, 2017

Abstract

Semiconductor devices having necked semiconductor bodies and methods of forming semiconductor bodies of varying width are described. For example, a semiconductor device includes a semiconductor body disposed above a substrate. A gate electrode stack is disposed over a portion of the semiconductor body to define a channel region in the semiconductor body under the gate electrode stack. Source and drain regions are defined in the semiconductor body on either side of the gate electrode stack. Sidewall spacers are disposed adjacent to the gate electrode stack and over only a portion of the source and drain regions. The portion of the source and drain regions under the sidewall spacers has a height and a width greater than a height and a width of the channel region of the semiconductor body.

First claim

What is claimed is:

1. A method of fabricating a semiconductor device, the method comprising:
forming a semiconductor body continuous with and protruding from a substrate;
forming a gate electrode stack over a portion of the semiconductor body to define a channel region in the semiconductor body under the gate electrode stack and source and drain regions in the semiconductor body on either side of the gate electrode stack; and
forming sidewall spacers adjacent to the gate electrode stack and over only a portion of the source and drain regions, wherein the portion of the source and drain regions under the sidewall spacers has a height and a width greater than a height and a width of the channel region of the semiconductor body, wherein forming the gate electrode stack comprises forming a sacrificial gate electrode stack, removing the sacrificial gate electrode stack, and forming a permanent gate electrode stack, and wherein forming the channel region comprises thinning a portion of the semiconductor body exposed subsequent to removing the sacrificial gate electrode stack and prior to forming the permanent gate electrode stack, wherein forming the channel region comprises forming a channel region having tapering regions, and wherein the tapering regions are rounded corner features.

2. The method of claim 1 , wherein the semiconductor body comprises silicon.

3. A method of fabricating a semiconductor device, the method comprising:
forming a hardmask pattern above a substrate, the hardmask pattern comprising a first region of fin forming features, each of a first width, and the hardmask pattern also comprising a second region of fin forming features, each of a second width approximately equal to the first width; and, subsequently,
forming and patterning a resist layer to cover the second region and expose the first region; and, subsequently,
etching the fin forming features of the first region to form thinned fin forming features, each of a third width less than the second width; and, subsequently,
removing the resist layer; and, subsequently,
transferring the hardmask pattern to the substrate to form a first region of fins, each of the third width, and to form a second region of fins, each of the second width; and, subsequently,
forming semiconductor devices from the fins of the first and second regions.

4. The method of claim 3 , wherein the substrate is a single-crystalline silicon substrate, and wherein transferring the hardmask pattern to the substrate comprises forming single crystalline silicon fins.

5. A method of fabricating a semiconductor device, the method comprising:
forming a semiconductor body;
forming a gate electrode stack over a portion of the semiconductor body to define a channel region in the semiconductor body under the gate electrode stack and source and drain regions in the semiconductor body on either side of the gate electrode stack; and
forming sidewall spacers adjacent to the gate electrode stack and over only a portion of the source and drain regions, wherein the portion of the source and drain regions under the sidewall spacers has a height and a width greater than a height and a width of the channel region of the semiconductor body, wherein forming the gate electrode stack comprises forming a sacrificial gate electrode stack, removing the sacrificial gate electrode stack, and forming a permanent gate electrode stack, and wherein forming the channel region comprises thinning a portion of the semiconductor body exposed subsequent to removing the sacrificial gate electrode stack and prior to forming the permanent gate electrode stack, wherein forming the channel region comprises forming a channel region having tapering regions, and wherein the tapering regions are rounded corner features.

6. The method of claim 5 , wherein the semiconductor body comprises silicon.

Assignees

• Sell Bernhard
• Intel Corp

Inventors

• Sell Bernhard

Classifications

• H10P50/693

  characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane · CPC title

• H10P50/642

  Chemical etching · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H01L29/6656

  Electricity · mapped topic

• H01L29/0847

  Electricity · mapped topic