Nonplanar device with thinned lower body portion and method of fabrication

Patent metadata

Field	Value
Publication number	US-9741809-B2
Application number	US-201514856490-A
Country	US
Kind code	B2
Filing date	Sep 16, 2015
Priority date	Oct 25, 2004
Publication date	Aug 22, 2017
Grant date	Aug 22, 2017

Abstract

A nonplanar semiconductor device having a semiconductor body formed on an insulating layer of a substrate. The semiconductor body has a top surface opposite a bottom surface formed on the insulating layer and a pair of laterally opposite sidewalls wherein the distance between the laterally opposite sidewalls at the top surface is greater than at the bottom surface. A gate dielectric layer is formed on the top surface of the semiconductor body and on the sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric layer on the top surface and sidewalls of the semiconductor body. A pair of source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.

First claim

We claim:

1. A nonplanar transistor, comprising:
a semiconductor body disposed above a substrate, the semiconductor body having a channel region comprising:
a top surface; and
a pair of laterally opposite sidewalls extending downward from the top surface;
an uppermost body portion adjacent the top surface and above a lowermost body portion, wherein a widest width of the uppermost body portion is located where the uppermost body portion meets the lowermost body portion, and wherein the laterally opposite sidewalls of the lowermost body portion taper continually inward downward from the uppermost body portion;
a gate dielectric layer formed on and in direct contact with the top surface and the sidewalls of the channel region including on and in direct contact with the laterally opposite sidewalls of the lowermost body portion which continually taper inward;
a gate electrode formed on the gate dielectric layer on the top surface and sidewalls of the channel region; and
a pair of source/drain regions on opposite sides of the channel region.

2. The nonplanar transistor of claim 1 , wherein the channel region is disposed on an insulating layer disposed on the substrate.

3. The nonplanar transistor of claim 1 , wherein the laterally opposite sidewalls of the lowermost body portion taper continually inward to meet at a substantially flat bottom surface of the channel region.

4. The nonplanar transistor of claim 1 , wherein the laterally opposite sidewalls of the lowermost body portion taper continually inward to meet at a point.

5. The nonplanar transistor of claim 1 , wherein a distance between the sidewalls at a bottom of the lowermost body portion is sufficiently small so as to improve the short channel effects of the transistor.

6. The nonplanar transistor of claim 1 , wherein the semiconductor body comprises silicon.

7. The nonplanar transistor of claim 1 , wherein the composition of the gate dielectric layer formed on the top surface is the same composition as the gate dielectric layer formed on the sidewalls.

8. The nonplanar transistor of claim 1 , wherein the gate dielectric layer is a continuous gate dielectric layer formed on and in direct contact with the top surface and the sidewalls of the channel region.

9. A method of fabricating a nonplanar transistor, the method comprising:
forming a semiconductor body above a substrate, the semiconductor body having a channel region comprising:
a top surface; and
a pair of laterally opposite sidewalls extending downward from the top surface;
an uppermost body portion adjacent the top surface and above a lowermost body portion, wherein a widest width of the uppermost body portion is located where the uppermost body portion meets the lowermost body portion, and wherein the laterally opposite sidewalls of the lowermost body portion taper continually inward downward from the uppermost body portion;
forming a gate dielectric layer on and in direct contact with the top surface and the sidewalls of the channel region including on and in direct contact with the laterally opposite sidewalls of the lowermost body portion which continually taper inward;
forming a gate electrode on the gate dielectric layer on the top surface and sidewalls of the channel region; and

forming a pair of source/drain regions on opposite sides of the channel region.

10. The method of claim 9 , wherein forming the semiconductor body comprises forming the channel region on an insulating layer.

11. The method of claim 9 , wherein forming the semiconductor body comprises forming a silicon body.

12. The method of claim 9 , wherein forming the gate dielectric layer comprises forming a same composition gate dielectric layer on the top surface and on the sidewalls.

13. The method of claim 9 , wherein forming the gate dielectric layer comprises forming a continuous gate dielectric layer on and in direct contact with the top surface and the sidewalls of the channel region.

Assignees

• Intel Corp

Inventors

• Shah Uday
• Doyle Brian S
• Brask Justin K
• Chau Robert S
• Letson Thomas A

Classifications

• H01L29/7853

  Electricity · mapped topic

• H01L27/0886

  Electricity · mapped topic

• H01L29/66795

  Electricity · mapped topic

• H01L21/845

  Electricity · mapped topic

• H01L21/823431

  Electricity · mapped topic