Semiconductor device and manufacturing method of semiconductor device

Patent metadata

Field	Value
Publication number	US-12520490-B2
Application number	US-202318338164-A
Country	US
Kind code	B2
Filing date	Jun 20, 2023
Priority date	Feb 6, 2023
Publication date	Jan 6, 2026
Grant date	Jan 6, 2026

Abstract

A semiconductor device includes a first gate structure including a plurality of first conductive layers and a plurality of first insulating layers that are alternately stacked; an isolation insulating layer located in the first gate structure, the isolation insulating layer including a first line portion extending in a first direction, a plurality of first protrusions protruding from the first line portion towards one side of the first line portion in a second direction, and a plurality of second protrusions protruding from the first line portion towards another side of the first line portion in an opposite direction to the first protrusions, wherein the second direction is orthogonal to the first direction; a plurality of first memory patterns, wherein one of the plurality of first memory patterns surrounds one of the plurality of first protrusions; and a plurality of first passivation patterns, wherein one of the plurality of first passivation patterns is located between the first line portion and one of the plurality of first memory patterns.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a first gate structure including a plurality of first conductive layers and a plurality of first insulating layers that are alternately stacked; an isolation insulating layer located in the first gate structure, the isolation insulating layer including a first line portion extending in a first direction, a plurality of first protrusions protruding from the first line portion in a second direction, and a plurality of second protrusions protruding from the first line portion in an opposite direction to the first protrusions, wherein the second direction intersects the first direction; a plurality of first memory patterns, wherein one of the plurality of first memory patterns surrounds one of the plurality of first protrusions; and a plurality of first passivation patterns, wherein one of the plurality of first passivation patterns is located between the first line portion and one of the plurality of first memory patterns.

2 . The semiconductor device of claim 1 , wherein one of the plurality of first conductive layers protrudes between the plurality of first memory patterns and extends between the plurality of first passivation patterns.

3 . The semiconductor device of claim 1 , further comprising:
a plurality of first channel patterns, wherein one of the plurality of first channel patterns surrounds one of the plurality of first protrusions, one of the plurality of first channel patterns being located between one of the plurality of first protrusion and one of the plurality of first memory patterns.

4 . The semiconductor device of claim 3 , wherein one of the plurality of first passivation patterns extends between the first line portion and one of the plurality of first channel patterns.

5 . The semiconductor device of claim 1 , further comprising:
a plurality of second memory patterns, wherein one of the plurality of second memory patterns surrounds one of the plurality of second protrusions; and a plurality of second passivation patterns, wherein one of the plurality of second passivation patterns is located between the first line portion and one of the plurality of second memory patterns.

6 . The semiconductor device of claim 5 , wherein one of the plurality of first conductive layers protrudes between the plurality of second memory patterns and extends between the plurality of second passivation patterns.

7 . The semiconductor device of claim 5 , further comprising:
a plurality of second channel patterns, wherein one of the plurality of second channel patterns surrounds one of the plurality of second protrusions, one of the plurality of second channel patterns being located between one of the plurality of second protrusion and one of the plurality of second memory patterns.

8 . The semiconductor device of claim 7 , wherein one of the plurality of second passivation patterns extends between the first line portion and one of the plurality of second channel patterns.

9 . The semiconductor device of claim 1 , further comprising:
a third memory pattern surrounding an end portion of the first line portion; and a third channel pattern located between the isolation insulating layer and the third memory pattern.

10 . The semiconductor device of claim 9 , wherein the third memory pattern extends to surround a first protrusion, among the plurality of first protrusions, and a second protrusion, among the plurality of second protrusions, which are adjacent to the end portion of the first line portion.

11 . The semiconductor device of claim 1 , further comprising:
a second gate structure including a plurality of second conductive layers and a plurality of second insulating layers that are alternately stacked; and an isolation structure located between the first gate structure and the second gate structure, the isolation structure including a dummy channel layer and a dummy memory layer surrounding the dummy channel layer.

12 . The semiconductor device of claim 11 , wherein the dummy channel layer comprises:
a second line portion located between the first gate structure and the second gate structure; a first protruding pattern protruding from the second line portion into the first gate structure; and a second protruding pattern protruding from the second line portion into the second gate structure.

Assignees

• Sk Hynix Inc

Inventors

• Kwak Rho Gyu
• Jang Jung Shik
• Park In Su
• Choi Seok Min
• Choi Won Geun
• Choi Jung Dal

Classifications

• H10B41/10 Primary

  characterised by the top-view layout · CPC title

• H10B41/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B43/10

  characterised by the top-view layout · CPC title

• H10B43/35

  with cell select transistors, e.g. NAND · CPC title

• H10B41/35

  with a cell select transistor, e.g. NAND · CPC title