Memory arrays with backside components and angled transistors

Patent metadata

Field	Value
Publication number	US-12520482-B2
Application number	US-202318325492-A
Country	US
Kind code	B2
Filing date	May 30, 2023
Priority date	Jun 29, 2022
Publication date	Jan 6, 2026
Grant date	Jan 6, 2026

Abstract

Memory arrays with backside components and angled transistors, and related assemblies and methods, are disclosed herein. A transistor is referred to as an “angled transistor” if a longitudinal axis of an elongated semiconductor structure of the transistor (e.g., a fin or a nanoribbon) is neither perpendicular nor parallel to any edges of front or back sides of a support structure (e.g., a die) over which the transistor is implemented. A component is referred to as a “backside component” if it is provided on the side of a semiconductor substrate that is opposite to the side over which the transistors of the memory arrays are provided. Memory arrays with backside components and angled transistors provide a promising way to increasing densities of memory cells on the limited real estate of semiconductor chips and/or decreasing adverse effects associated with continuous scaling of IC components.

First claim

The invention claimed is:

1 . An integrated circuit (IC) device, comprising:
a substrate; memory cells, an individual memory cell comprising a transistor and a capacitor; and memory control lines, comprising a plurality of bitlines (BLs) and a plurality of wordlines (WLs), wherein:
pair of the memory cells coupled to a single BL of the plurality of BLs are along a single elongated structure comprising one or more semiconductor materials and have a single source or drain (S/D) region shared between the transistors of the pair,
gates of the transistors of the pair are coupled to different WLs of the plurality of WLs,
the transistors of the memory cells are on a front side of the substrate,
at least one of a set of the capacitors of the memory cells and a set of the BLs is on a back side of the substrate, and
a longitudinal axis of the elongated structure is diagonal with respect to an edge of the substrate.

2 . The IC device according to claim 1 , wherein:
the memory control lines further include a plurality of platelines (PLs), the elongated structure is one of a plurality of elongated structures, the pair is a first pair, second pair of the memory cells coupled to a single PL of the plurality of PLs are along different elongated structures of the plurality of elongated structures, and gates of the transistors of the second pair are coupled to different WLs of the plurality of WLs, and the longitudinal axis of the elongated structure is diagonal with respect to the edge of the substrate for each of the plurality of elongated structures.

3 . The IC device according to claim 1 , wherein:
the plurality of the WLs is in a layer over the front side of the substrate, the set of the BLs is on the back side of the substrate, an individual BL of the set of BLs includes a liner material on sidewalls of the BL and a fill material between the sidewalls of the BL, and in a transverse cross-section of the BL, a width of the BL at a first distance from the layer is smaller than a width of the BL at a second distance from the layer when the first distance is smaller than the second distance.

4 . The IC device according to claim 3 , wherein:
the set of the capacitors is on the back side of the substrate, in a cross-section of an individual capacitor along a plane perpendicular to the layer, a width of the capacitor at a third distance from the layer is smaller than a width of the capacitor at a fourth distance from the layer when the third distance is smaller than the fourth distance.

5 . The IC device according to claim 1 , wherein:
the plurality of the WLs is in a layer over the front side of the substrate, the set of the BLs is on the back side of the substrate, and in a transverse cross-section of the BL, a width of the BL at a first distance from the layer is larger than a width of the BL at a second distance from the layer when the first distance is smaller than the second distance.

6 . The IC device according to claim 5 , wherein:
the set of the capacitors is on the back side of the substrate, in a cross-section of an individual capacitor along a plane perpendicular to the layer, a width of the capacitor at a third distance from the layer is smaller than a width of the capacitor at a fourth distance from the layer when the third distance is smaller than the fourth distance.

7 . The IC device according to claim 1 , wherein:
the plurality of the WLs is in a layer over the front side of the substrate, the set of the capacitors is on the back side of the substrate, and in a cross-section of an individual capacitor along a plane perpendicular to the layer, a width of the capacitor at a first distance from the layer is smaller than a width of the capacitor at a second distance from the layer when the first distance is smaller than the second distance.

8 . The IC device according to claim 7 , wherein:
the set of the BLs is on the back side of the substrate, and in a transverse cross-section of an individual BL of the set of BLs, a width of the BL at a third distance from the layer is smaller than a width of the BL at a fourth distance from the layer when the third distance is smaller than the fourth distance.

9 . The IC device according to claim 8 , wherein the BL includes a liner material on sidewalls of the BL and a fill material between the sidewalls of the BL.

10 . The IC device according to claim 7 , wherein:
the set of the BLs is on the back side of the substrate, in a transverse cross-section of an individual BL of the set of BLs, a width of the BL at a third distance from the layer is larger than a width of the BL at a fourth distance from the layer when the third distance is smaller than the fourth distance.

11 . An integrated circuit (IC) device, comprising:
a memory cell comprising a transistor and a capacitor coupled to the transistor; and a control line coupled to a first source or drain (S/D) region of the transistor, wherein:
the control line is in a first layer,
the first layer includes an insulator material,
the control line includes a liner material on sidewalls of the control line and a fill material between the sidewalls of the control line,
a channel region of the transistor is in a second layer,
the capacitor is in a third layer and is coupled to a second S/D region of the transistor,
the second layer is between the first layer and the third layer,
a width of the capacitor at a first distance from the second layer is smaller than a width of the capacitor at a second distance from the second layer when the first distance from the second layer is smaller than the second distance from the second layer, and
in a transverse cross-section of the control line, a width of the control line at a third distance from the second layer is smaller than a width of the control line at a fourth distance from the second layer when the third distance from the second layer is smaller than the fourth distance from the second layer.

12 . The IC device according to claim 11 , wherein, in a transverse cross-section of the channel region, a width of the channel region at a first distance from the first layer is larger than a width of the channel region at a second distance from the first layer when the first distance from the first layer is smaller than the second distance from the first layer.

13 . The IC device according to claim 11 , further comprising:
a support structure; and an elongated structure comprising one or more semiconductor materials, wherein:
the memory cell and the control line are over the support structure,
the channel region is a portion of the elongated structure, and
an angle between an edge of the support structure and a projection of the elongated structure onto a plane of the support structure is between about 10 degrees and 80 degrees.

14 . An integrated circuit (IC) device, comprising:
a first layer comprising parallel control lines extending in a first direction; a second layer comprising parallel elongated structures extending in a second direction, the elongated structures comprising one or more semiconductor materials; a third layer comprising capacitors; and transistors having channel regions in different portions of the elongated structures, wherein:
the second layer is between the first layer and the third layer,
for at least a subset of the elongated structures, an individual elongated structure includes two transistors sharing a single first source or drain (S/D) region, the first S/D region coupled to one of the control lines,
second S/D regions of different ones of the transistors are coupled to diffe

Assignees

• Intel Corp

Inventors

• Sharma Abhishek A
• Suthram Sagar
• Ghani Tahir
• Murthy Anand S
• Weber Cory E
• Mehandru Rishabh
• Gomes Wilfred
• Ranade Pushkar Sharad

Classifications

• H10B12/033

  the capacitor extending over the transistor · CPC title

• H10B12/05 Primary

  Making the transistor · CPC title

• H10B12/482

  Bit lines · CPC title

• H10D1/716

  having vertical extensions · CPC title

• H10B53/30

  characterised by the memory core region · CPC title