Apparatuses and systems for offset cross field-effect transistors

Patent metadata

Field	Value
Publication number	US-12513943-B2
Application number	US-202217974643-A
Country	US
Kind code	B2
Filing date	Oct 27, 2022
Priority date	Oct 27, 2022
Publication date	Dec 30, 2025
Grant date	Dec 30, 2025

Abstract

The disclosed integrated circuit for offset cross field effect transistors can include a first transistor include a first channel oriented in a first direction; an oxide layer adjacent to the first transistor; and a second transistor adjacent to the oxide layer. The second transistor can include a second channel that is oriented in a direction orthogonal to the first direction, and the first channel and the second channel can be laterally offset such that the second channel does not cross over the first channel. Various other apparatuses, systems, and methods are also disclosed.

First claim

What is claimed is:

1 . An integrated circuit comprising:
a first transistor comprising a first channel oriented in a first direction and a first gate; an oxide layer adjacent to the first transistor; and a second transistor adjacent to the oxide layer, wherein:
the second transistor comprises:
a second channel that is oriented in a direction orthogonal to the first direction; and
a second gate extending in the first direction such that the second gate crosses over the first gate; and

the first channel and the second channel are laterally offset such that the second channel does not cross over the first channel.

2 . The integrated circuit of claim 1 , wherein:
the first channel comprises a first nanosheet; the second channel comprises a second nanosheet; the first transistor is a gate-all-around device; and the second transistor is a gate-all-around device.

3 . The integrated circuit of claim 2 , wherein the first transistor further comprises a third channel comprising a third nanosheet.

4 . The integrated circuit of claim 2 , wherein the first gate extends in a second direction.

5 . The integrated circuit of claim 4 , further comprising a vertical gate contact coupled to the first gate and to the second gate.

6 . The integrated circuit of claim 1 , wherein a first doping polarity of the first channel is an opposite polarity of a second doping polarity of the second channel.

7 . The integrated circuit of claim 1 , wherein the second channel is formed on a wafer that is bonded with the oxide layer.

8 . The integrated circuit of claim 1 , wherein the first transistor comprises a first metal sidewall source and a first metal sidewall drain.

9 . The integrated circuit of claim 1 , wherein:
the second transistor comprises a second metal sidewall source and a second metal sidewall drain; and the second metal sidewall source is directly connected to a front metal layer by a contact.

10 . A system comprising:
physical memory comprising computer-executable instructions; and an integrated circuit configured to execute the computer-executable instructions, the integrated circuit comprising:
a first transistor comprising a first channel oriented in a first direction and a first gate;
an oxide layer adjacent to the first transistor; and
a second transistor adjacent to the oxide layer, wherein:
the second transistor comprises:
a second channel that is oriented in a direction orthogonal to the first direction; and
a second gate extending in the first direction such that the second gate crosses over the first gate; and
the first channel and the second channel are laterally offset such that the second channel does not cross over the first channel.

11 . The system of claim 10 , wherein:
the first channel comprises a first nanosheet; the second channel comprises a second nanosheet; the first transistor is a gate-all-around device; and the second transistor is a gate-all-around device.

12 . The system of claim 11 , wherein the first transistor further comprises a third channel comprising a third nanosheet.

13 . The system of claim 11 , wherein the first gate extends in a second direction.

14 . The system of claim 13 , further comprising a vertical gate contact coupled to the first gate and to the second gate.

15 . The system of claim 10 , wherein a first doping polarity of the first channel is an opposite polarity of a second doping polarity of the second channel.

16 . The system of claim 10 , wherein the second channel is formed on a wafer that is bonded with the oxide layer.

17 . The system of claim 10 , wherein the first transistor comprises a first metal sidewall source and a first metal sidewall drain.

18 . The system of claim 17 , further comprising a third transistor adjacent to the first transistor, wherein no diffusion break structure is interposed between the first transistor and the third transistor.

19 . The system of claim 18 , further comprising at least one of:
an air gap between the first transistor and the third transistor; or a stress layer between the first transistor and the third transistor.

20 . A method comprising:
placing, in an integrated circuit, a first transistor and a second transistor; forming the first transistor with a first channel oriented in a first direction and a first gate; forming an oxide layer adjacent to the first transistor; and forming the second transistor adjacent to the oxide layer, wherein:
the second transistor comprises:
a second channel that is oriented in a second direction orthogonal to the first direction; and
a second gate extending in the first direction such that the second gate crosses over the first gate; and

the first channel and the second channel are laterally offset such that the second channel does not cross over the first channel.

Assignees

• Advanced Micro Devices Inc

Inventors

• Schultz Richard

Classifications

• H10D62/213

  Channel regions of field-effect devices · CPC title

• H10D62/118

  Nanostructure semiconductor bodies · CPC title

• H10D84/0149

  Manufacturing their interconnections or electrodes, e.g. source or drain electrodes · CPC title

• H10D84/016

  the components including vertical IGFETs · CPC title

• H10D30/6735 Primary

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title