Power rails for stacked semiconductor device

Patent metadata

Field	Value
Publication number	US-2022270935-A1
Application number	US-202217663608-A
Country	US
Kind code	A1
Filing date	May 16, 2022
Priority date	Aug 19, 2020
Publication date	Aug 25, 2022
Grant date	—

Abstract

The present disclosure describes a method to form a stacked semiconductor device with power rails. The method includes forming the stacked semiconductor device on a first surface of a substrate. The stacked semiconductor device includes a first fin structure, an isolation structure on the first fin structure, and a second fin structure above the first fin structure and in contact with the isolation structure. The first fin structure includes a first source/drain (S/D) region, and the second fin structure includes a second S/D region. The method also includes etching a second surface of the substrate and a portion of the first S/D region or the second S/D region to form an opening. The second surface is opposite to the first surface. The method further includes forming a dielectric barrier in the opening and forming an S/D contact in the opening.

First claim

What is claimed is:

1 . A method, comprising:
forming a stacked semiconductor device on a first surface of a substrate, wherein the stacked semiconductor device comprises a source/drain (S/D) region; etching a second surface of the substrate and a portion of the S/D region to form an opening, wherein the second surface is opposite to the first surface; and forming, in the opening, a S/D contact structure in contact with the S/D region.

2 . The method of claim 1 , further comprising:
replacing the substrate with a dielectric layer; forming, in the dielectric layer, an interconnect connected to the S/D contact structure; and connecting the interconnect to a power supply.

3 . The method of claim 2 , wherein the replacing the substrate comprises:
removing the substrate; and forming the dielectric layer on the stacked semiconductor device, wherein the dielectric layer comprises silicon oxide.

4 . The method of claim 1 , further comprising:
replacing the substrate with a dielectric layer; forming, in the dielectric layer, an interconnect connected to the S/D contact structure; and connecting the interconnect to ground.

5 . The method of claim 1 , further comprising:
forming a bonding layer on the first surface of the substrate; bonding an additional substrate to the bonding layer; flipping the substrate on top of the additional substrate; and removing a portion of the substrate.

6 . The method of claim 1 , further comprising:
depositing a dielectric layer in the opening; removing a portion of the dielectric layer on the S/D region; and forming the S/D contact structure on the dielectric layer.

7 . The method of claim 1 , wherein the forming the SID contact structure comprises:
forming a silicide layer on the S/D region; and forming a metal contact structure on the silicide layer.

8 . The method of claim 1 , wherein the portion of the S/D region comprises an epitaxial stop layer.

9 . A method, comprising:
forming, on a first surface of a substrate, a first device having a first source/drain (SID) region stacked over a second device having a second S/D region; etching a second surface of the substrate and a portion of the first S/D region to form a first opening, wherein the second surface is opposite to the first surface; forming, in the first opening, a first S/D contact structure in contact with the first S/D region; etching the second surface of the substrate and a portion of the second S/D region to form a second opening; and forming, in the second opening, a second SID contact structure in contact with the second S/D region.

10 . The method of claim 9 , further comprising:
replacing the substrate with a dielectric layer; forming a first interconnect connected to the first SID contact structure and a second interconnect connected to the second S/D contact structure; and connecting the first interconnect to a power supply and the second interconnect to ground.

11 . The method of claim 10 , wherein the replacing the substrate comprises:
removing the substrate; and forming the dielectric layer over the first and second devices, wherein the dielectric layer comprises silicon oxide.

12 . The method of claim 9 , further comprising:
forming a bonding layer on the first surface of the substrate; bonding an additional substrate to the bonding layer; flipping the substrate on top of the additional substrate; and removing a portion of the substrate.

13 . The method of claim 9 , further comprising:
depositing a dielectric layer in the first opening; removing a portion of the dielectric layer on the first S/D region; and forming the first S/D contact structure on the dielectric layer.

14 . The method of claim 9 , wherein the forming the first S/D contact structure comprises:
forming a silicide layer on the first S/D region; and forming a metal contact structure on the silicide layer.

15 . The method of claim 9 , wherein the portion of the first S/D region comprises a first epitaxial stop layer and the portion of the second S/D region comprises a second epitaxial stop layer.

16 . The method of claim 9 , further comprising forming an isolation structure between the first and second devices.

17 . An integrated circuit, comprising:
a stacked semiconductor device on a first surface of a substrate, wherein the stacked semiconductor device comprises a first device stacked over a second device and wherein the second device comprises a source/drain (S/D) region; a S/D contact structure on a second surface of the substrate and connected to the S/D region, wherein the second surface is opposite to the first surface; and a dielectric barrier surrounding the S/D contact structure.

18 . The integrated circuit of claim 17 , further comprising a gate contact structure on the first surface of the substrate, wherein the gate contact structures is connected to a gate structure of the first device.

19 . The integrated circuit of claim 17 , further comprising an isolation structure between the first and second devices.

20 . The integrated circuit of claim 17 , wherein the S/D contact structure comprises a silicide layer on the SID region and a metal contact structure on the silicide layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Yang Chansyun David
• Chang Keh-Jeng
• Yang Chan-Lon

Classifications

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10P90/1922

  using silicon etch back techniques, e.g. BESOI or ELTRAN · CPC title

• H10W20/427

  Power or ground buses · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title