Semiconductor device

Patent metadata

Field	Value
Publication number	US-2022173100-A1
Application number	US-202117536413-A
Country	US
Kind code	A1
Filing date	Nov 29, 2021
Priority date	Nov 30, 2020
Publication date	Jun 2, 2022
Grant date	—

Abstract

A semiconductor device includes a substrate, an N-well area formed in the substrate, a first P-channel metal oxide semiconductor (PMOS) transistor having active regions formed in the N-well area, and a first N-channel metal oxide semiconductor (NMOS) transistor having active regions formed in the substrate. The first NMOS transistor includes a first N-type active region overlapping each of the substrate and the N-well area, when viewed from above a plane parallel to a top surface of the substrate.

First claim

1 . A semiconductor device comprising:
a substrate; an N-well area formed in the substrate; a first P-channel metal oxide semiconductor (PMOS) transistor having active regions formed in the N-well area; and a first N-channel metal oxide semiconductor (NMOS) transistor having active regions formed in the substrate, wherein the first NMOS transistor includes a first N-type active region overlapping each of the substrate and the N-well area, when viewed from above a plane parallel to a top surface of the substrate.

2 . The semiconductor device of claim 1 , wherein:
the first N-type active region extends in a first direction parallel to the plane, such that a first portion of the first N-type active region overlaps the N-well area when viewed from above the plane and a second portion of the first N-type active region adjacent to the first portion in the first direction overlaps the substrate without overlapping the N-well area when viewed from above the plane.

3 . The semiconductor device of claim 2 , wherein a body bias of the first PMOS transistor is provided directly through the first N-type active region.

4 . The semiconductor device of claim 2 , wherein, when viewed from above the plane, the first portion of the first N-type active region, which overlaps the N-well area, is a well guard-ring of the N-well area.

5 . The semiconductor device of claim 2 , wherein a doping concentration of the first N-type active region is higher than a doping concentration of the N-well area.

6 . The semiconductor device of claim 2 , wherein the first NMOS transistor further includes a second N-type active region formed in the substrate.

7 . The semiconductor device of claim 6 , wherein a first length of the first N-type active region in the first direction is equal to a second length of the second N-type active region in the first direction.

8 . The semiconductor device of claim 6 , wherein a first length of the first N-type active region in the first direction is longer than a second length of the second N-type active region in the first direction.

9 . The semiconductor device of claim 6 , wherein, when viewed from above the plane, a shape of the first N-type active region is different from a shape of the second N-type active region.

10 . The semiconductor device of claim 6 , wherein a first depth of the first N-type active region in a third direction is different from a second depth of the second N-type active region in the third direction, and
wherein the third direction is a direction perpendicular to the plane.

11 . The semiconductor device of claim 6 , wherein a merged area of the first N-type active region, which is placed in the N-well area when viewed from above the plane, has a third depth in a third direction, and a remaining area of the first N-type active region other than the merged area has a fourth depth in the third direction,
wherein the third depth is different from the fourth depth, and wherein the third direction is a direction perpendicular to the plane.

12 . The semiconductor device of claim 6 , wherein the first N-type active region includes at least one first N + implant area, and
wherein the second N-type active region includes at least one second N + implant area.

13 . The semiconductor device of claim 12 , wherein at least a portion of the at least one first N + implant area overlaps the N-well area when viewed from above the plane.

14 . The semiconductor device of claim 12 , wherein a number of the at least one first N + implant area is different from a number of the at least one second N + implant area.

15 . The semiconductor device of claim 12 , wherein, when viewed from above the plane, a shape of the at least one first N + implant area is different from a shape of the at least one second N + implant area.

16 . (canceled)

17 . The semiconductor device of claim 1 , further comprising:
an oxide layer formed on the substrate, wherein a first portion of the oxide layer, which overlaps the N-well area when viewed from above the plane, has a first height, and wherein a portion of the first portion, which overlaps the first N-type active region when viewed from above the plane, has a third height different from the first height.

18 . The semiconductor device of claim 1 , wherein the first PMOS transistor includes:
a first P-type active region and a second P-type active region formed in the N-well area; and a first gate formed on the N-well area between the first P-type active region and the second P-type active region, wherein the first NMOS transistor further includes: a second N-type active region formed in the substrate; and a second gate formed on the substrate between the first N-type active region and the second N-type active region, wherein the first N-type active region overlapping the N-well area is a body bias node of the first PMOS transistor.

19 . The semiconductor device of claim 18 , further comprising:
a first contact plug electrically connected to the second P-type active region; a second contact plug electrically connected to the first N-type active region; and a metal line configured to electrically connect the first contact plug and the second contact plug.

20 . A semiconductor device comprising:
a substrate; an N-well area formed in the substrate; a first P-type active region formed in the N-well area; a second P-type active region formed in the N-well area; a first gate formed on the N-well area between the first P-type active region and the second P-type active region; a body bias node formed in the N-well area; a first N-type active region formed in the substrate; a second N-type active region formed in the substrate; and a second gate formed on the substrate between the first N-type active region and the second N-type active region, wherein the body bias node and the first N-type active region are formed of a single continuous active region.

21 . A semiconductor device comprising:
a substrate; an N-well area formed in the substrate; a PMOS transistor including active regions formed in the N-well area; and an NMOS transistor including active regions formed in the substrate and including a first N-type active region, wherein the first N-type active region is continuously formed in the N-well area and in a portion of the substrate horizontally adjacent to the N-well area, is used as a source area or a drain area of the NMOS transistor, and is configured to directly provide a body bias of the PMOS transistor to the N-well area.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Ahreum
• Kim Sunghoon
• Byeon Daeseok

Classifications

• H10W90/20

  Configurations of stacked chips · CPC title

• H10W90/00

  Package configurations · CPC title

• H10D89/10

  Integrated device layouts · CPC title

• H10D84/857

  comprising an N-type well but not a P-type well · CPC title

• H10D84/0191

  Manufacturing their doped wells · CPC title