Laser ablation for die separation to reduce laser splash and electronic device

US12512416B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12512416-B2
Application numberUS-202217826764-A
CountryUS
Kind codeB2
Filing dateMay 27, 2022
Priority dateMay 27, 2022
Publication dateDec 30, 2025
Grant dateDec 30, 2025

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method includes performing a laser ablation process that removes a portion of a wafer to form a trench in a scribe region between adjacent die regions of the wafer, the trench extending from a first side of the wafer toward an opposite second side of the wafer, the trench extending through a metallization structure and an active circuit portion of the wafer, and a bottom of the trench spaced apart from the second side of the wafer. The method also includes performing a wafer expansion process that separates individual semiconductor dies from the wafer after the laser ablation process.

First claim

Opening claim text (preview).

What is claimed is: 1 . A method of fabricating an electronic device, the method comprising: performing a laser ablation process that removes a portion of a wafer to form a trench in a scribe region between adjacent die regions of the wafer, the trench extending from a first side of the wafer toward an opposite second side of the wafer, the trench extending through a metallization structure and an active circuit portion of the wafer, and a bottom of the trench spaced apart from the second side of the wafer; after the laser ablation process, performing a wafer probe test that tests circuitry of the active circuit portion of the wafer; after the wafer probe test, performing a wafer expansion process that separates individual semiconductor dies from the wafer; and packaging one of the semiconductor dies in a package structure to form an electronic device. 2 . The method of claim 1 , further comprising, after the wafer probe test and before the wafer expansion process, performing a grinding process on the second side of the wafer. 3 . The method of claim 2 , wherein the laser ablation process is a multi-pass process that uses multiple passes of an ablation laser to successively increase the depth of the trench and/or a lateral width of the trench. 4 . The method of claim 3 , wherein the laser ablation process forms the trench to an average depth distance of 20 μm or more and 25 μm or less from the first side of the wafer toward the second side of the wafer. 5 . The method of claim 2 , wherein the laser ablation process forms the trench to an average depth distance of 20 μm or more and 25 μm or less from the first side of the wafer toward the second side of the wafer. 6 . The method of claim 1 , wherein the laser ablation process is a multi-pass process that uses multiple passes of an ablation laser to successively increase the depth of the trench and/or a lateral width of the trench. 7 . The method of claim 6 , wherein the laser ablation process forms the trench to an average depth distance of 20 μm or more and 25 μm or less from the first side of the wafer toward the second side of the wafer. 8 . The method of claim 7 , wherein the laser ablation process forms the trench to an average width of 20 μm or more and 40 μm or less between the adjacent die regions of the wafer. 9 . The method of claim 1 , wherein the laser ablation process forms the trench to an average depth distance of 20 μm or more and 25 μm or less from the first side of the wafer toward the second side of the wafer. 10 . The method of claim 9 , wherein the laser ablation process forms the trench to an average width of 20 μm or more and 40 μm or less between the adjacent die regions of the wafer. 11 . The method of claim 1 , wherein the laser ablation process forms the trench to an average width of 20 μm or more and 40 μm or less between the adjacent die regions of the wafer. 12 . A method of separating semiconductor dies from a wafer, the method comprising: performing a laser ablation process that removes a portion of a wafer to form a trench in a scribe region between adjacent die regions of the wafer, the trench extending from a first side of the wafer toward an opposite second side of the wafer, the trench extending through a metallization structure and an active circuit portion of the wafer, and a bottom of the trench spaced apart from the second side of the wafer; and after the laser ablation process, performing a wafer expansion process that separates individual semiconductor dies from the wafer. 13 . The method of claim 12 , wherein the laser ablation process forms the trench to an average depth distance of 20 μm or more and 25 μm or less from the first side of the wafer toward the second side of the wafer. 14 . A method of fabricating an electronic device, the method comprising: performing a laser ablation process that removes a portion of a wafer to form a trench in a scribe region between adjacent die regions of the wafer, the trench extending from a first side of the wafer toward an opposite second side of the wafer, the trench extending through a metallization structure and an active circuit portion of the wafer, and a bottom of the trench spaced apart from the second side of the wafer; after the laser ablation process, performing a wafer probe test that tests circuitry of the active circuit portion of the wafer; and after the wafer probe test, performing a wafer expansion process. 15 . The method of claim 14 , further comprising, after the wafer probe test and before the wafer expansion process, performing a grinding process on the second side of the wafer. 16 . The method of claim 15 , wherein the laser ablation process is a multi-pass process that uses multiple passes of an ablation laser to successively increase the depth of the trench and/or a lateral width of the trench. 17 . The method of claim 16 , wherein the laser ablation process forms the trench to an average depth distance of 20 μm or more and 25 μm or less from the first side of the wafer toward the second side of the wafer. 18 . The method of claim 15 , wherein the laser ablation process forms the trench to an average depth distance of 20 μm or more and 25 μm or less from the first side of the wafer toward the second side of the wafer. 19 . The method of claim 14 , wherein the laser ablation process is a multi-pass process that uses multiple passes of an ablation laser to successively increase the depth of the trench and/or a lateral width of the trench. 20 . The method of claim 19 , wherein the laser ablation process forms the trench to an average depth distance of 20 μm or more and 25 μm or less from the first side of the wafer toward the second side of the wafer. 21 . The method of claim 20 , wherein the laser ablation process forms the trench to an average width of 20 μm or more and 40 μm or less between the adjacent die regions of the wafer. 22 . The method of claim 14 , wherein the laser ablation process forms the trench to an average depth distance of 20 μm or more and 25 μm or less from the first side of the wafer toward the second side of the wafer. 23 . The method of claim 22 , wherein the laser ablation process forms the trench to an average width of 20 μm or more and 40 μm or less between the adjacent die regions of the wafer. 24 . The method of claim 14 , wherein the laser ablation process forms the trench to an average width of 20 μm or more and 40 μm or less between the adjacent die regions of the wafer.

Assignees

Inventors

Classifications

  • for identification or tracking · CPC title

  • Bond wires · CPC title

  • Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

  • with electromagnetic radiation, e.g. laser annealing (laser cutting H10P54/20) · CPC title

  • between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

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What does patent US12512416B2 cover?
A method includes performing a laser ablation process that removes a portion of a wafer to form a trench in a scribe region between adjacent die regions of the wafer, the trench extending from a first side of the wafer toward an opposite second side of the wafer, the trench extending through a metallization structure and an active circuit portion of the wafer, and a bottom of the trench spaced …
Who is the assignee on this patent?
Texas Instruments Inc
What technology area does this patent fall under?
Primary CPC classification H10W46/00. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Dec 30 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 4 related publications on this page (citations in our corpus or others sharing the same primary CPC).