Back end of line structure for improved current density in HR devices

Patent metadata

Field	Value
Publication number	US-12512406-B2
Application number	US-202217820020-A
Country	US
Kind code	B2
Filing date	Aug 16, 2022
Priority date	Aug 16, 2022
Publication date	Dec 30, 2025
Grant date	Dec 30, 2025

Abstract

A semiconductor device is described herein. The semiconductor device generally includes a metal fabrication layer disposed on a substrate. The semiconductor device generally includes a dielectric layer having a first plurality of vias aligned with a first metallization region of the metal fabrication layer and a second plurality of vias aligned with a second metallization region of the metal fabrication layer, the dielectric layer disposed on top of the metal fabrication layer. The semiconductor device generally includes a metal layer disposed on the dielectric layer and having a plurality of metal routings, each of the metal regions disposed over both the first metallization region and the second metallization region, each of the plurality of metal routings have a same width. The semiconductor device generally includes an insulation layer disposed on the metal layer, the insulation layer having a plurality of openings to the metal routings of the metal layer.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a metal fabrication layer disposed on a substrate, the metal fabrication layer having a first metallization region and a second metallization region; a dielectric layer having a first plurality of vias aligned with the first metallization region of the metal fabrication layer and a second plurality of vias aligned with the second metallization region of the metal fabrication layer, the dielectric layer disposed on top of the metal fabrication layer; a metal layer disposed on the dielectric layer, the metal layer having a plurality of metal routings, each of the plurality of metal routings disposed over both the first metallization region of the metal fabrication layer and the second metallization region of the metal fabrication layer, each of the plurality of metal routings has a same width; and an insulation layer disposed on the metal layer, the insulation layer having a plurality of openings to the plurality of metal routings of the metal layer.

2 . The semiconductor device of claim 1 , wherein the first metallization region is coupled to a first node, and the second metallization region is coupled to a second node.

3 . The semiconductor device of claim 1 , further comprising a plurality of copper posts, each copper post coupled to a metal routing of the plurality of metal routings of the metal layer.

4 . The semiconductor device of claim 3 , wherein each of the plurality of copper posts comprises a metal contact coupled to the respective metal routing through a respective opening of the plurality of openings of the insulation layer.

5 . The semiconductor device of claim 4 , wherein each opening comprises an area less than a surface area of the respective copper post.

6 . The semiconductor device of claim 4 , wherein the metal contact is disposed in the respective opening, and each copper post contacts the insulation layer.

7 . The semiconductor device of claim 1 , wherein the first plurality of vias comprises a first subset of vias and a second subset of vias, the first subset of vias disposed under a first metal region of the plurality of metal routings, the second subset of vias disposed under a second metal region of the plurality of metal routings, the second metal region separated from the first metal region by a third metal region, and wherein spacing between the first subset of vias and the second subset of vias is greater than a width of the first metal region.

8 . The semiconductor device of claim 7 , wherein the spacing between the first subset of vias and the second subset of vias is greater than 90 um.

9 . The semiconductor device of claim 1 , wherein the first plurality of vias comprises a first subset of vias and a second subset of vias, wherein the first metallization region comprises a first metallization subregion and a second metallization subregion, the first subset of vias coupled to the first metallization subregion, the second subset of vias coupled to the second metallization subregion, the first subset of vias and the second subset of vias coupled to a same metallization region of the metal layer, the first metallization subregion and the second metallization subregion separated by the second metallization region, and wherein a number of vias of the first subset of vias is equal to a number of vias of the second subset of vias.

10 . The semiconductor device of claim 1 , wherein the first plurality of vias are disposed at intersections between the plurality of metal routings and the first metallization region.

11 . The semiconductor device of claim 1 , wherein each of the plurality of metal routings of the metal layer comprises a width of 58 um.

12 . The semiconductor device of claim 1 , wherein sides of each of the plurality of metal routings are linear.

13 . The semiconductor device of claim 1 , wherein a thickness of the metal fabrication layer is smaller than a thickness of the metal layer.

Assignees

• Texas Instruments Inc

Inventors

• Harrison William
• Ankamah-Kusi Sylvester
• Tang Yiqi
• Murugan Rajen M

Classifications

• H10W72/252

  comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/244

  relative to underlying supporting features, e.g. bond pads, RDLs or vias · CPC title

• H10W20/063

  by forming conductive members before forming protective insulating material · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/43 Primary

  Layouts of interconnections · CPC title