X-line routing for dense multi-chip-package interconnects

Patent metadata

Field	Value
Publication number	US-9240377-B2
Application number	US-201414579073-A
Country	US
Kind code	B2
Filing date	Dec 22, 2014
Priority date	Oct 31, 2012
Publication date	Jan 19, 2016
Grant date	Jan 19, 2016

Abstract

X-line routing arrangements for dense multi-chip-package interconnects are described. In an example, an electronic signal routing structure includes a substrate. A plurality of layers of conductive traces is disposed above the substrate. A first pair of ground traces is disposed in a first of the plurality of layers of conductive traces. A signal trace is disposed in a second of the plurality of layers of conductive traces, below the first layer. A second pair of ground traces is disposed in a third of the plurality of layers of conductive traces, below the first layer. The first and second pairs of ground traces and the signal trace provide an X-pattern routing from a cross-sectional perspective.

First claim

What is claimed is:

1. An electronic signal routing structure, comprising:
a substrate;
a plurality of layers of conductive traces disposed above the substrate;
a first pair of ground traces disposed in a first of the plurality of layers of conductive traces, wherein the first pair of ground traces is a first pair of co-planar ground traces;
a signal trace disposed in a second of the plurality of layers of conductive traces, below the first layer; and
a second pair of ground traces disposed in a third of the plurality of layers of conductive traces, below the first layer, wherein the first and second pairs of ground traces and the signal trace provide an X-pattern routing from a cross-sectional perspective, wherein the second pair of ground traces is a second pair of co-planar ground traces, wherein the first pair of co-planar ground traces is vertically aligned with the second pair of co-planar ground traces, and wherein, from a vertical perspective, the traces of the first and second pairs of co-planar ground traces do not overlap with the signal trace.

2. The electronic signal routing structure of claim 1 , wherein the plurality of layers of conductive traces is disposed in one or more dielectric layers disposed above the substrate.

3. The electronic signal routing structure of claim 1 , wherein the substrate is a bulk crystalline silicon substrate, and the plurality of layers of conductive traces comprises copper traces.

4. The electronic signal routing structure of claim 1 , further comprising: additional signal traces and ground traces providing additional X-pattern routing.

5. The electronic signal routing structure of claim 4 , wherein a half-pitch offset is provided horizontally between signal traces across adjacent layers of conductive traces having signal traces therein.

6. An electronic signal routing structure, comprising:
a substrate;
a plurality of layers of conductive traces disposed above the substrate;
a first pair of ground traces disposed in a first of the plurality of layers of conductive traces;
a signal trace disposed in a second of the plurality of layers of conductive traces, below the first layer;
a second pair of ground traces disposed in a third of the plurality of layers of conductive traces, below the first layer, wherein the first and second pairs of ground traces and the signal trace provide an X-pattern routing from a cross-sectional perspective; and
additional signal traces and ground traces providing additional X-pattern routing, wherein a half-pitch offset is provided horizontally between signal traces across adjacent layers of conductive traces having signal traces therein.

7. The electronic signal routing structure of claim 6 , wherein the first pair of ground traces is a first pair of co-planar ground traces, and the second pair of ground traces is a second pair of co-planar ground traces.

8. The electronic signal routing structure of claim 7 , wherein the first pair of co-planar ground traces is vertically aligned with the second pair of co-planar ground traces.

9. The electronic signal routing structure of claim 6 , wherein the plurality of layers of conductive traces is disposed in one or more dielectric layers disposed above the substrate.

10. The electronic signal routing structure of claim 6 , wherein the substrate is a bulk crystalline silicon substrate, and the plurality of layers of conductive traces comprises copper traces.

Assignees

• Qian Zhiguo
• Aygun Kemal
• Intel Corp

Inventors

• Qian Zhiguo
• Aygun Kemal

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W70/63

  Vias, e.g. via plugs · CPC title

• H10W90/401

  characterised by multiple insulating or insulated package substrates, interposers or RDLs · CPC title

• H10W90/00

  Package configurations · CPC title