Metallisation for semiconductor device

Patent metadata

Field	Value
Publication number	US-10748847-B2
Application number	US-201514849469-A
Country	US
Kind code	B2
Filing date	Sep 9, 2015
Priority date	Oct 8, 2014
Publication date	Aug 18, 2020
Grant date	Aug 18, 2020

Abstract

The present disclosure relates to a semiconductor device comprising a metallisation stack. The metallisation stack may include a first metallisation layer and a second metallisation layer. The first metallisation layer may be electrically connected to the second metallisation layer by a two or more stacked inter-metal vias.

First claim

The invention claimed is:

1. A semiconductor device comprising:
a semiconductor device die;
an inter-layer dielectric layer provided directly on the semiconductor device die; and
a metallisation stack provided directly on the inter-layer dielectric layer, the metallisation stack comprising a first discrete metallisation layer and a second discrete metallisation layer separated by an inter-metal dielectric layer, wherein the first discrete metallisation layer is electrically connected to the second discrete metallisation layer by a plurality of directly connected stacked inter-metal vias that are vertically stacked between the first discrete metallization layer and the second discrete metallization layer, wherein the first discrete metallisation layer of the metallisation stack is separated from the semiconductor device die by the inter-layer dielectric layer, and wherein the inter-metal dielectric layer does not include a semiconductor layer.

2. The semiconductor device of claim 1 , wherein the first discrete metallisation layer is configured to connect to the semiconductor device die and the second discrete metallisation layer is configured to form bond pads and to distribute the current to a device die.

3. The semiconductor device of claim 1 , further comprising:
a contact via configured to electrically connect the first discrete metallisation layer to an ohmic contact of a semiconductor die.

4. The semiconductor device of claim 1 , wherein a vertical thickness of the first discrete metallisation layer is less than a vertical thickness of the second discrete metallisation layer.

5. The semiconductor device of claim 1 , wherein the plurality of stacked inter-metal vias comprises a first inter-metal via and a second inter-metal via, and wherein the first inter-metal via abuts the second inter-metal via.

6. The semiconductor device of claim 1 , wherein the inter-metal dielectric layer comprises a first inter-metal dielectric layer directly on the first metallization layer and a second inter-metal dielectric layer directly on the first inter-metal dielectric layer; and
wherein the second metallization layer is directly on the second inter-metal dielectric layer.

7. The semiconductor device of claim 6 , wherein the plurality of stacked inter-metal vias comprises a first inter-metal via in the first inter-metal dielectric layer and a second inter-metal via that are directly in the second inter-metal dielectric layer.

8. An electrostatic discharge (ESD) protection device comprising the semiconductor device of claim 1 .

9. A data transfer line comprising the ESD protection device of claim 8 .

10. The method of manufacturing a semiconductor device having a metallisation stack, the method comprising:
forming a first metallisation layer on an inter-layer dielectric layer that directly contacts the inter-layer dielectric; and
forming the first metallisation layer and a second metallisation layer separated by an inter-metal dielectric layer and contacting the first metallisation layer to the second metallisation layer by a plurality of directly connected stacked inter-metal vias such that the first metallisation layer is electrically connected to the second metallisation layer by the plurality of stacked inter-metal vias, wherein the inter-metal dielectric layer does not include a semiconductor layer;
wherein the plurality of stacked inter-metal vias are vertically stacked between the first metallization layer and the second metallization layer, and
wherein the first metallisation layer of the metallisation stack is separated from the semiconductor device die by the inter-layer dielectric layer.

11. A method of manufacturing the semiconductor device of claim 10 , wherein the first metallisation layer is formed to connect to a semiconductor die and the second metallisation layer forms bond pads and to distribute current to a device die.

12. The method of manufacturing the semiconductor device of claim 10 , further comprising forming a contact via arranged to electrically connect the first metallisation layer to a contact of a semiconductor die.

13. The method of manufacturing the semiconductor device of claim 10 , wherein a vertical thickness of the first metallisation layer is less than a vertical thickness of the second metallisation layer.

14. The method of manufacturing the semiconductor device of claim 10 , wherein the plurality of stacked inter-metal are formed as first inter-metal via and a second inter metal via.

15. The method of manufacturing the semiconductor device of claim 14 , wherein first inter-metal via and a second inter metal via are formed to be directly connected without an intermediate connection.

Assignees

• Nexperia BV

Inventors

• Huiskamp Paul
• Notermans Godfried Henricus Josephus

Classifications

• H10W72/29

  Bond pads specially adapted therefor · CPC title

• H10W72/9232

  with additional elements interposed between layers · CPC title

• H10W72/252

  comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/242

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W20/4441

  the principal metal being a refractory metal · CPC title