Thermal dispersion layer in programmable metallization cell

Patent metadata

Field	Value
Publication number	US-12507601-B2
Application number	US-202318362041-A
Country	US
Kind code	B2
Filing date	Jul 31, 2023
Priority date	Jun 29, 2018
Publication date	Dec 23, 2025
Grant date	Dec 23, 2025

Abstract

Some embodiments relate to an integrated chip including a first conductive structure over a substrate. A first dielectric layer is on the first conductive structure. A second dielectric layer is on the first dielectric layer, where thermal conductivities of the first and second dielectric layers are different from one another. A second conductive structure is over the second dielectric layer.

First claim

What is claimed is:

1 . An integrated chip, comprising:
a first conductive structure overlying a substrate; a dielectric layer on the first conductive structure; a data storage layer over and contacting the dielectric layer, wherein thermal conductivities of the dielectric layer and the data storage layer are different from one another, wherein the dielectric layer comprises a first material and the data storage layer comprises a second material different from the first material, wherein the dielectric layer vertically separates a bottommost surface of the data storage layer from a top surface of the first conductive structure, wherein the thermal conductivity of the dielectric layer is greater than 100 W/m-K; and a second conductive structure over the data storage layer.

2 . The integrated chip of claim 1 , wherein a thermal conductivity of the first conductive structure is greater than the thermal conductivity of the data storage layer and less than the thermal conductivity of the dielectric layer.

3 . The integrated chip of claim 1 , wherein a height of the dielectric layer is less than a height of the data storage layer.

4 . The integrated chip of claim 3 , wherein a height of the first conductive structure is greater than the height of the dielectric layer.

5 . The integrated chip of claim 1 , wherein upper opposing sidewalls of the data storage layer are spaced between outer opposing sidewalls of the dielectric layer.

6 . The integrated chip of claim 1 , wherein the dielectric layer continuously laterally extends along and contacts the bottommost surface of the data storage layer between outer sidewalls of the data storage layer.

7 . The integrated chip of claim 1 , further comprising:
a first conductive via overlying the second conductive structure, wherein the first conductive via is disposed within a memory region; and a second conductive via disposed within a logic region laterally adjacent to the memory region, wherein a top surface of the second conductive via is aligned with a top surface of the first conductive via, and wherein a bottom surface of the second conductive via is vertically below a bottom surface of the first conductive structure.

8 . An integrated chip, comprising:
a memory cell overlying a substrate, wherein the memory cell comprises a dielectric layer disposed between a first conductive structure and a second conductive structure, a metal layer disposed between the second conductive structure and the dielectric layer, and a thermal dissipation layer disposed directly between the dielectric layer and the first conductive structure, wherein the thermal dissipation layer comprises aluminum nitride, silicon carbide, beryllium oxide, or boron nitride; and wherein opposing sidewalls of the metal layer are aligned with first opposing sidewalls of the dielectric layer, wherein opposing sidewalls of the thermal dissipation layer are aligned with opposing sidewalls of the first conductive structure.

9 . The integrated chip of claim 8 , wherein a thermal conductivity of the first conductive structure is less than a thermal conductivity of the thermal dissipation layer.

10 . The integrated chip of claim 9 , wherein a thermal conductivity of the metal layer is greater than the thermal conductivity of the thermal dissipation layer.

11 . The integrated chip of claim 8 , wherein the first opposing sidewalls of the dielectric layer are spaced between the opposing sidewalls of the thermal dissipation layer.

12 . The integrated chip of claim 8 , further comprising:
a sidewall spacer structure disposed around the second conductive structure and the metal layer, wherein opposing sidewalls of the sidewall spacer structure are aligned with the opposing sidewalls of the thermal dissipation layer.

13 . The integrated chip of claim 8 , wherein the memory cell is configured to switch between a high resistance state and a low resistance state, wherein in the high resistance state a lower conductive bridge is disposed within the thermal dissipation layer and the dielectric layer, wherein a top surface of the lower conductive bridge is vertically below a top surface of the dielectric layer by a non-zero distance, and wherein in the low resistance state an upper conductive bridge extends from the top surface of the lower conductive bridge to the metal layer.

14 . An integrated chip, comprising:
a bottom electrode over a substrate; a thermal dissipation layer over the bottom electrode, wherein outer sidewalls of the thermal dissipation layer are aligned with outer sidewalls of the bottom electrode, wherein a thermal conductivity of the thermal dissipation layer is greater than a thermal conductivity of the bottom electrode; a first dielectric layer over the thermal dissipation layer, wherein the thermal dissipation layer is disposed between a top surface of the bottom electrode and a bottom surface of the first dielectric layer; a top electrode over the first dielectric layer; a metal layer between the top electrode and the first dielectric layer; and a sidewall spacer along sidewalls of the top electrode and the metal layer, wherein the sidewall spacer directly overlies a top surface of the thermal dissipation layer.

15 . The integrated chip of claim 14 , wherein outer sidewalls of the metal layer are spaced between the outer sidewalls of the thermal dissipation layer.

16 . The integrated chip of claim 14 , wherein a thickness of the thermal dissipation layer is less than a thickness of the first dielectric layer.

17 . The integrated chip of claim 14 , further comprising:
a second dielectric layer over the top electrode and surrounding the first dielectric layer, wherein the second dielectric layer contacts the outer sidewalls of the bottom electrode and has a thermal conductivity less than the thermal conductivity of the thermal dissipation layer.

18 . The integrated chip of claim 14 , wherein the thermal conductivity of the thermal dissipation layer is at least two times greater than a thermal conductivity of the top electrode.

19 . The integrated chip of claim 14 , wherein the sidewall spacer contacts the top surface of the thermal dissipation layer and an upper surface of the first dielectric layer.

20 . The integrated chip of claim 14 , wherein the bottom electrode and the top electrode comprise a metal-containing material different from that of the metal layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• JIANG Fa-Shen
• Lin Hsing-Lien

Classifications

• H10N70/8613

  Heating or cooling means other than resistive heating electrodes, e.g. heater in parallel · CPC title

• H10N70/8265

  on sidewalls of dielectric structures, e.g. mesa-shaped or cup-shaped devices · CPC title

• H10N70/841

  Electrodes · CPC title

• H10N70/063

  by etching of pre-deposited switching material layers, e.g. lithography · CPC title

• G11C13/0011 Primary

  comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs] · CPC title