Embedded memory device with a composite top electrode

Patent metadata

Field	Value
Publication number	US-9954166-B1
Application number	US-201615362153-A
Country	US
Kind code	B1
Filing date	Nov 28, 2016
Priority date	Nov 28, 2016
Publication date	Apr 24, 2018
Grant date	Apr 24, 2018

Abstract

A memory cell with a composite top electrode is provided. A bottom electrode is disposed over a substrate. A switching dielectric having a variable resistance is disposed over the bottom electrode. A capping layer is disposed over the switching dielectric. A composite top electrode is disposed over and abutting the capping layer. The composite top electrode comprises a tantalum nitride (TaN) layer and a titanium nitride (TiN) film disposed directly on the tantalum nitride layer. By having the disclosed composite top electrode, an interfacial oxidized layer is eliminated or less formed when exposing the composite top electrode for top electrode via formation, thereby improving RC properties between the top electrode and the top electrode via. A method for manufacturing the memory cell is also provided.

First claim

What is claimed is:

1. A memory cell, comprising:
a bottom electrode disposed over a substrate;
a switching dielectric disposed over the bottom electrode and having a variable resistance;
a capping layer disposed over the switching dielectric; and
a composite top electrode disposed over and abutting the capping layer, wherein the composite top electrode comprises a tantalum nitride (TaN) layer and a titanium nitride (TiN) film disposed directly on the tantalum nitride layer;
wherein the TiN film has a first nitrogen concentration and the TaN layer has a second nitrogen concentration, the first nitrogen concentration being greater than the second nitrogen concentration.

2. The memory cell of claim 1 , wherein the TiN film of the composite top electrode has a molar ratio of nitrogen:titanium substantially equal to 1.

3. The memory cell of claim 1 , wherein the TaN layer of the composite top electrode has a major portion and an upper portion disposed on the major portion, wherein the major portion has a molar ratio of nitrogen:tantalum being in a range of from about 3:10 to 1:2 and the upper portion has a decreasing molar ratio of nitrogen:tantalum that decreases to substantially zero at a top surface of the upper portion.

4. The memory cell of claim 1 , further comprising:
a bottom metallization line coupled to the bottom electrode through a conductive bottom electrode via; and
a top metallization line coupled to the top composite electrode through a top electrode via, the top electrode via comprising a bulk copper having bottom and sidewall surfaces surrounded by a tantalum glue layer or tantalum nitride glue layer.

5. The memory cell of claim 4 , wherein the bottom electrode via comprises a lower portion narrower than an upper portion, wherein the upper portion has a sidewall vertically aligned with sidewalls of the bottom electrode and the switching dielectric.

6. The memory cell of claim 5 , further comprising:
a hard mask disposed over the composite top electrode; and
a sidewall spacer disposed on an upper surface of the switching dielectric and extended upwardly along the capping layer, the composite top electrode, and the hard mask.

7. The memory cell of claim 6 , further comprising:
a lower dielectric layer surrounding the lower portion of the bottom electrode via; and
an upper dielectric layer disposed on the lower dielectric layer and extending along sidewalls of the upper portion of the bottom electrode via, the bottom electrode, the switching dielectric, the sidewall spacer and the hard mask, and further extending on an upper surface of the hard mask.

8. The memory cell of claim 1 , wherein sidewalls of the capping layer and sidewalls of the composite top electrode are aligned with one another and not aligned with a sidewall of the bottom electrode.

9. An embedded memory cell, comprising:
a bottom interconnect structure comprising a bottom metallization line surrounded by a bottom interlayer dielectric (ILD) layer;
a bottom electrode via disposed on the bottom interconnect structure and surrounded by a lower dielectric layer;
a bottom electrode electrically connected to the bottom metallization line by the bottom electrode via;
a resistive switching element disposed over the bottom electrode and a capping layer disposed over the resistive switching element; and
a composite top electrode disposed over the capping layer, and including a lower TaN top electrode layer and an upper TiN top electrode layer having a smaller thickness than the lower TaN top electrode layer;
wherein the upper TiN top electrode layer has a molar ratio of nitrogen greater than that of the lower TaN top electrode layer.

10. The embedded memory cell of claim 9 , further comprising:
a sidewall spacer disposed alongside the capping layer and the composite top electrode; and
an upper dielectric layer disposed on the lower dielectric layer and lining the bottom electrode, the resistive switching element and the sidewall spacer.

11. The embedded memory cell of claim 10 , further comprising:
a top electrode via disposed through the upper dielectric layer and electrically connected to the upper TiN top electrode layer of the composite top electrode.

12. The embedded memory cell of claim 11 , wherein the top electrode via comprises a bulk copper having bottom and sidewall surfaces surrounded by a tantalum glue layer or tantalum nitride glue layer.

13. The embedded memory cell of claim 9 , wherein the lower TaN top electrode layer of the composite top electrode comprises a tantalum nitride layer having a major portion and an upper portion disposed on the major portion, wherein the major portion has a molar ratio of nitrogen:tantalum being in a range of from about 3:10 to 1:2 and the upper portion has a molar ratio of nitrogen:tantalum that decreases to substantially zero at a top surface of the upper portion.

14. The embedded memory cell of claim 9 , wherein the lower TaN top electrode layer of the composite top electrode comprises a tantalum nitride layer having a molar ratio of nitrogen:tantalum in a range of from about 3:10 to 1:2.

15. The embedded memory cell of claim 9 , wherein the upper TiN top electrode layer of the composite top electrode comprises a titanium nitride layer having a molar ratio of nitrogen:titanium substantially equal to 1.

16. A method for manufacturing a memory cell, the method comprising:
forming a multi-layer stack comprising a bottom electrode layer, a switching dielectric layer over the bottom electrode layer, a capping layer over the switching dielectric layer, a lower TaN top electrode layer over the capping layer, an upper TiN top electrode layer over the lower TaN top electrode layer, and a hard mask over the upper TiN top electrode layer, wherein the upper TiN top electrode layer has a greater nitrogen molar ratio than the lower TaN top electrode layer;
performing a first etch to pattern the upper TiN top electrode layer, the lower TaN top electrode layer, and the capping layer according to the hard mask;
forming a sidewall spacer alongside the upper TiN top electrode layer, the lower TaN top electrode layer, and the capping layer; and
performing a second etch to pattern the switching dielectric layer and the bottom electrode layer according to the sidewall spacer and the hard mask.

17. The method of claim 16 , wherein the lower TaN top electrode layer is formed by sputtering a tantalum target to deposit on the capping layer while a nitrogen gas is applied.

18. The method of claim 17 , wherein the upper TiN top electrode layer is formed by sputtering a titanium target to deposit on the lower TaN top electrode layer while the nitrogen gas is applied, during which a flow rate of the nitrogen gas is applied at a higher flow rate than during forming the lower TaN top electrode layer.

19. The method of claim 16 , wherein the upper TiN top electrode layer is formed to be thinner than the lower TaN top electrode layer.

20. The method of claim 16 , further including:
forming an upper dielectric layer lining the bottom electrode layer, the switching dielectric layer, and the sidewall spacer;
forming a top interlayer dielectric (ILD) layer over and around the upper dielectric layer; and
forming a top metallization line over the top ILD layer and a top electrode via extending between the upper TiN top electrode layer and the top metallization line.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lin Hsing-Lien
• Trinh Hai-Dang
• Chang Yao-Wen

Classifications

• H01L27/2436

  Electricity · mapped topic

• H01L45/124

  Electricity · mapped topic

• H01L45/1253 Primary

  Electricity · mapped topic

• H01L45/1608

  Electricity · mapped topic

• H10N70/24 Primary

  based on migration or redistribution of ionic species, e.g. anions, vacancies · CPC title