Three-terminal synapse device and method of operating the same
US-9224946-B2 · Dec 29, 2015 · US
US2017133584A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2017133584-A1 |
| Application number | US-201615084149-A |
| Country | US |
| Kind code | A1 |
| Filing date | Mar 29, 2016 |
| Priority date | Nov 5, 2015 |
| Publication date | May 11, 2017 |
| Grant date | — |
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A conductive-bridging random access memory is provided. The conductive-bridging random access memory includes a bottom electrode layer on a semiconductor substrate, an electrical resistance switching layer on the bottom electrode layer, a barrier layer on the electrical resistance switching layer, a top electrode layer on the barrier layer, and a high thermal-conductive material layer between the bottom electrode layer and the barrier layer. The high thermal-conductive material layer has a thermal conductivity in a range of 70-5000 W/mK.
Opening claim text (preview).
What is claimed is: 1 . A conductive-bridging random access memory, comprising: a semiconductor substrate; a bottom electrode layer formed on the semiconductor substrate; an electrical resistance switching layer formed on the bottom electrode layer; a barrier layer formed on the electrical resistance switching layer; a top electrode layer formed on the barrier layer; and a high thermal-conductive material layer formed between the bottom electrode layer and the barrier layer, wherein the high thermal-conductive material layer has a thermal conductivity in a range of 70-5000 W/mK. 2 . The conductive-bridging random access memory as claimed in claim 1 , wherein the high thermal-conductive material layer is formed between the bottom electrode layer and the electrical resistance switching layer. 3 . The conductive-bridging random access memory as claimed in claim 1 , wherein the high thermal-conductive material layer is formed between the electrical resistance switching layer and the barrier layer. 4 . The conductive-bridging random access memory as claimed in claim 1 , wherein the high thermal-conductive material layer comprises nitride, oxide, carbide, metal, alloy, or combinations thereof. 5 . The conductive-bridging random access memory as claimed in claim 4 , wherein the high thermal-conductive material layer comprises aluminium nitride, beryllium oxide, gold, platinum, nickel, tungsten, iron, zinc, graphite, carbon nanotubes or combinations thereof. 6 . The conductive-bridging random access memory as claimed in claim 1 , wherein the high thermal-conductive material layer has a thickness in a range of 1-1000 nm. 7 . The conductive-bridging random access memory as claimed in claim 1 , wherein a thermal conductivity of the electrical resistance switching layer is lower than that of the high thermal-conductive material layer by 50 W/mK. 8 . The conductive-bridging random access memory as claimed in claim 1 , wherein the high thermal-conductive material layer has an electrical conductivity in a range of 9×10 6 −1×10 8 S/m. 9 . The conductive-bridging random access memory as claimed in claim 1 , wherein the high thermal-conductive material layer has an electrical conductivity in a range of 5×10 −15 −5×10 −14 S/m. 10 . The conductive-bridging random access memory as claimed in claim 1 , wherein a difference between a coefficient of linear thermal expansion of the high thermal-conductive material layer and a coefficient of linear thermal expansion of the electrical resistance switching layer is equal to or lower than 50×10 −6 1/K.
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