Semiconductor device contact structures and methods of fabricating thereof

Patent metadata

Field	Value
Publication number	US-12507459-B2
Application number	US-202318519714-A
Country	US
Kind code	B2
Filing date	Nov 27, 2023
Priority date	Jul 30, 2021
Publication date	Dec 23, 2025
Grant date	Dec 23, 2025

Abstract

Methods and devices including an air gap adjacent a contact element extending to a source/drain feature of a device are described. Some embodiments of the method include depositing a dummy layer, which is subsequently removed to form the air gap. The dummy layer and subsequent air gap may be formed after a SAC dielectric layer such as silicon nitride is formed over an adjacent metal gate structure.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a metal gate structure disposed over a substrate, wherein a first dielectric layer is formed along sidewalls of the metal gate structure; a source/drain feature adjacent the metal gate structure; a contact element extending to the source/drain feature; a second dielectric layer surrounding the contact element, wherein the second dielectric layer is surrounding the contact element in a top view such that the second dielectric layer encircles the contact element; a contact etch stop layer disposed over the first dielectric layer and the second dielectric layer; and an air gap over the source/drain feature and surrounding the second dielectric layer, wherein in the top view, the air gap is encircling the second dielectric layer and the contact element, and wherein in a cross-sectional view the air gap has a first portion on a first side of the contact element and a second portion on an opposing side of the contact element, wherein the first portion is defined by a first sidewall, a second sidewall opposing the first sidewall, and upper edge defined by a bottommost surface of the contact etch stop layer, and wherein:
the first sidewall extending from the source/drain feature to the upper edge and the second sidewall extending from the source/drain feature to the upper edge, wherein the first sidewall is defined by the first dielectric layer and the second sidewall is defined by the second dielectric layer,
the second portion of the air gap has a third sidewall extending from the source/drain feature to another upper edge defined by the contact etch stop layer and a fourth sidewall extending from the source/drain feature to the another upper edge, wherein third sidewall is defined by the second dielectric layer and the fourth sidewall has a first portion defined by the first dielectric layer and a second portion defined by a third dielectric layer.

2 . The semiconductor device of claim 1 , wherein the air gap extends a first distance from a top surface of the substrate to the upper edge and the another upper edge and the metal gate structure extends a second distance from the top surface of the substrate, the first distance being greater than the second distance.

3 . The semiconductor device of claim 1 , wherein the contact etch stop layer also disposed over the metal gate structure, and the contact element.

4 . The semiconductor device of claim 3 , wherein the contact etch stop layer interfaces the first dielectric layer.

5 . The semiconductor device of claim 1 , wherein the third dielectric layer has an uppermost surface interfacing an etch stop layer defining the upper edge of the air gap.

6 . The semiconductor device of claim 1 , wherein the third dielectric layer is disposed on the first dielectric layer.

7 . The semiconductor device of claim 1 , wherein the first sidewall, second sidewall, third sidewall, and fourth sidewall are substantially vertical.

8 . A semiconductor device, comprising:
a metal gate structure disposed over a substrate; a spacer layer, wherein a first sidewall of the spacer layer is formed on a sidewall of the metal gate structure; a first dielectric layer formed on a second sidewall of the spacer layer, wherein the second sidewall of the spacer layer is opposing the first sidewall of the spacer layer; a source/drain feature adjacent the metal gate structure; a contact element extending to the source/drain feature; a second dielectric layer surrounding the contact element; and an air gap interposing the second dielectric layer and the first dielectric layer in a top view and wherein the air gap surrounds the contact element in the top view, wherein the air gap in a cross-sectional view includes a first vertically extending edge and a second vertically extending edge, wherein the first vertically extending edge is defined in its entirety by the first dielectric layer and the second vertically extending edge includes a first portion defined by the first dielectric layer and a second portion above the first portion defined by another dielectric material.

9 . The semiconductor device of claim 8 , wherein the metal gate structure extends to a first height, the spacer layer extends to a second height, and the first dielectric layer extends to a third height.

10 . The semiconductor device of claim 9 , wherein the third height is greater than the second height and the second height greater than the first height.

11 . The semiconductor device of claim 8 , wherein the source/drain feature extends under the second dielectric layer.

12 . The semiconductor device of claim 8 , wherein a silicide portion of the source/drain feature interfaces the contact element.

13 . The semiconductor device of claim 8 , wherein the air gap exposes a top surface of the source/drain feature.

14 . The semiconductor device of claim 8 , wherein the another dielectric material is a third dielectric layer formed over the first dielectric layer.

15 . The semiconductor device of claim 14 , wherein the air gap includes a third vertically extending edge and a fourth vertically extending edge in the cross-sectional view, wherein the third vertically extending edge and the fourth vertically extending edge are each defined by the second dielectric layer.

16 . A semiconductor device, comprising:
a gate structure disposed over a substrate; a self-aligned contact (SAC) dielectric layer disposed over the gate structure a spacer layer interfacing sidewalls of the gate structure, wherein the SAC dielectric layer extends over an upper surface of the spacer layer and along a sidewall of the spacer layer; a source/drain feature, wherein the source/drain feature includes a silicide region; a contact element extending to the silicide region of the source/drain feature; a dielectric layer surrounding and interfacing sidewalls of the contact element; and an air gap interposing the dielectric layer and the spacer layer in a cross-sectional view and surrounding the contact element in a top view, wherein the air gap has an uppermost edge lower than the uppermost edge of the SAC dielectric layer.

17 . The semiconductor device of claim 16 , further comprising:
another dielectric layer between the spacer layer and the air gap.

18 . The semiconductor device of claim 17 , wherein the air gap extends from the another dielectric layer to the dielectric layer.

19 . The semiconductor device of claim 16 , wherein the air gap extends from a surface of the source/drain feature to an etch stop layer defining a top edge of the air gap.

20 . The semiconductor device of claim 19 , wherein the etch stop layer extends over the dielectric layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wu I-Wen
• Lee Chen-Ming
• Yang Fu-Kai
• Wang Mei-Yun

Classifications

• H10W20/0765

  the thin functional dielectric layers being temporary, e.g. sacrificial layers · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/076

  in via holes or trenches · CPC title

• H10W20/46

  comprising air gaps · CPC title

• H10W20/072

  of dielectric parts comprising air gaps · CPC title