Semiconductor device and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-12501678-B2
Application number	US-202217849754-A
Country	US
Kind code	B2
Filing date	Jun 27, 2022
Priority date	Apr 12, 2022
Publication date	Dec 16, 2025
Grant date	Dec 16, 2025

Abstract

A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a channel layer, a gate element on the channel layer, and source/drain elements at least partly embedded in the channel layer. The source/drain elements are on opposite sides of the gate element. The source/drain elements include a metal element and a lower silicide element between the metal element and the channel layer. The lower silicide element has a hydrogen content less than 2 at %.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a channel layer; a gate element on the channel layer; source/drain elements at least partly embedded in the channel layer and on opposite sides of the gate element; and a passivation layer on the channel layer, wherein the source/drain elements comprise a metal element, a lower silicide element between the metal element and the channel layer, and an upper silicide element above the passivation layer and the lower silicide element, the lower silicide element has a hydrogen content less than 2 at %, the metal element and the lower silicide element comprise different materials, and a sidewall of the metal element between the upper silicide element and the lower silicide element contacts the passivation layer.

2 . The semiconductor device according to claim 1 , wherein lower silicide element is separated from the upper silicide element.

3 . The semiconductor device according to claim 2 , wherein the passivation layer extends to cover a first sidewall, a second sidewall opposite to the first sidewall and an upper surface connected between the first sidewall and the second sidewall of the gate element.

4 . The semiconductor device according to claim 3 , further comprising a barrier layer between the channel layer and the gate element, wherein the sidewall of the metal element is above the barrier layer.

5 . The semiconductor device according to claim 1 , further comprising a barrier layer between the channel layer and the gate element, wherein an upper surface of the lower silicide element is above an upper surface of the barrier layer.

6 . The semiconductor device according to claim 1 , wherein the source/drain elements comprises two upper silicide elements, the lower silicide element is below the upper silicide elements, the lower silicide element and the upper silicide elements are separated from each other.

7 . The semiconductor device according to claim 6 , wherein the upper silicide elements are approximately at the same level.

8 . The semiconductor device according to claim 1 , wherein the lower silicide element of the source/drain elements comprises titanium silicide.

9 . The semiconductor device according to claim 1 , wherein the lower silicide element of the source/drain elements comprises aluminum.

10 . The semiconductor device according to claim 1 , wherein the metal element of the source/drain elements is free of gold and comprising aluminum.

11 . The semiconductor device according to claim 1 , wherein the hydrogen content of the lower silicide element of the source/drain elements is less than 1.5 at %.

12 . The semiconductor device according to claim 1 , wherein the lower silicide element of the source/drain elements has a nitrogen content less than 5 at %.

13 . The semiconductor device according to claim 1 , wherein the hydrogen content of the lower silicide element of the source/drain elements is less than 0.6 at %.

14 . The semiconductor device according to claim 1 , further comprising a barrier layer between the channel layer and the gate element, wherein a sidewall of the barrier layer is covered by the lower silicide element.

15 . The semiconductor device according to claim 14 , wherein a thickness of the lower silicide element is greater than a thickness of the barrier layer.

16 . The semiconductor device according to claim 14 , wherein an upper surface of the lower silicide element contacting the metal element is above an upper surface of the barrier layer.

17 . A semiconductor device, comprising:
a channel layer; a gate element on the channel layer; source/drain elements at least partly embedded in the channel layer and on opposite sides of the gate element; and a passivation layer on the channel layer, wherein the source/drain elements comprise a metal element, a lower silicide element between the metal element and the channel layer, and an upper silicide element above the passivation layer and the lower silicide element, the lower silicide element has a nitrogen content less than 5 at %, the metal element and the lower silicide element comprise different materials, and a sidewall of the metal element between the upper silicide element and the lower silicide element contacts the passivation layer.

Assignees

• United Microelectronics Corp

Inventors

• Lin da-jun
• Yeh Chih-Tung
• Tsai Fu-Yu
• Tsai Bin-Siang

Classifications

• H10D64/0116

  to Group III-V semiconductors · CPC title

• H10W74/137

  the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence) · CPC title

• H10D64/256

  for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673) · CPC title

• H10D64/01

  Manufacture or treatment · CPC title

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title