Semiconductor substrate and semiconductor device
US-2018175186-A1 · Jun 21, 2018 · US
US11264492B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-11264492-B2 |
| Application number | US-201916533812-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 7, 2019 |
| Priority date | Jul 9, 2019 |
| Publication date | Mar 1, 2022 |
| Grant date | Mar 1, 2022 |
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A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a barrier layer on the buffer layer; forming a hard mask on the barrier layer; performing an implantation process through the hard mask to form a doped region in the barrier layer and the buffer layer; removing the hard mask and the barrier layer to form a first trench; forming a gate dielectric layer on the hard mask and into the first trench; forming a gate electrode on the gate dielectric layer; and forming a source electrode and a drain electrode adjacent to two sides of the gate electrode.
Opening claim text (preview).
What is claimed is: 1. A high electron mobility transistor (HEMT), comprising: a buffer layer on a substrate; a barrier layer on the buffer layer; a gate electrode on the barrier layer; a gate dielectric layer between the barrier layer and the gate electrode; a doped region under the gate dielectric layer and overlapping the barrier layer and the buffer layer, wherein two sidewalls of the doped region are aligned with two sidewalls of the gate electrode; a hard mask between the gate dielectric layer and the barrier layer, wherein a sidewall of the gate dielectric layer is aligned with a sidewall of the hard mask and a width of a bottom surface of the doped region is greater than a width of a bottom surface of the gate dielectric layer and equal to a width of a top surface the gate electrode; and a source electrode and a drain electrode adjacent to two sides of the gate electrode on the buffer layer. 2. The HEMT of claim 1 , wherein the doped region comprises a U-shape.
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