HEMT and method of adjusting electron density of 2DEG

Patent metadata

Field	Value
Publication number	US-11239327-B2
Application number	US-201916513699-A
Country	US
Kind code	B2
Filing date	Jul 16, 2019
Priority date	Jun 25, 2019
Publication date	Feb 1, 2022
Grant date	Feb 1, 2022

Abstract

A high electron mobility transistor (HEMT) includes a gallium nitride layer. An aluminum gallium nitride layer is disposed on the gallium nitride layer, wherein the aluminum gallium nitride layer comprises a tensile stress. A source electrode and a drain electrode are disposed on the aluminum gallium nitride layer. A gate electrode is disposed on the aluminum gallium nitride layer between the source electrode and the drain electrode. At least one silicon oxide layer is embedded in the aluminum gallium nitride layer, wherein the silicon oxide layer is formed by a flowable chemical vapor deposition, and the silicon oxide layer increases the tensile stress in the aluminum gallium nitride layer.

First claim

What is claimed is:

1. A high electron mobility transistor (HEMT), comprising:
a gallium nitride layer;
an aluminum gallium nitride layer disposed on the gallium nitride layer, wherein the aluminum gallium nitride layer comprises a tensile stress;
a source electrode and a drain electrode disposed on the aluminum gallium nitride layer;
a gate electrode disposed on the aluminum gallium nitride layer between the source electrode and the drain electrode; and
a plurality of silicon oxide layers embedded in the aluminum gallium nitride layer, wherein each of the plurality of silicon oxide layers is free from protruding a top surface of the aluminum gallium nitride layer, sizes of the plurality of silicon oxide layers are the same, the plurality of silicon oxide layers are formed by a flowable chemical vapor deposition, and each of the plurality of silicon oxide layers increases the tensile stress in the aluminum gallium nitride layer.

2. The HEMT of claim 1 , wherein a top surface of each of the silicon oxide layers is aligned with the aluminum gallium nitride layer.

3. The HEMT of claim 1 , wherein one of the plurality of silicon oxide layers is disposed in the aluminum gallium nitride layer directly under the source electrode, in the aluminum gallium nitride layer directly under the drain electrode, or in the aluminum gallium nitride layer between the aluminum gallium nitride layer directly under the source electrode and the aluminum gallium nitride layer directly under the drain electrode.

4. The HEMT of claim 1 , wherein each of the plurality of silicon oxide layers comprises a compressive stress.

5. The HEMT of claim 1 , wherein a thickness of each of the plurality of silicon oxide layers is not larger than a thickness of the aluminum gallium nitride layer.

6. A high electron mobility transistor (HEMT) comprising:
a gallium nitride layer;
an aluminum gallium nitride layer disposed on the gallium nitride layer, wherein the aluminum gallium nitride layer comprises a tensile stress;
a source electrode and a drain electrode disposed on the aluminum gallium nitride layer;
a gate electrode disposed on the aluminum gallium nitride layer between the source electrode and the drain electrode; and
at least one stressor embedded in the aluminum gallium nitride layer, wherein the stressor decreases the tensile stress in the aluminum gallium nitride layer.

7. The HEMT of claim 6 , wherein a top surface of the stressor is aligned with the aluminum gallium nitride layer.

8. The HEMT of claim 6 , wherein the stressor is disposed in the aluminum gallium nitride layer directly under the drain electrode, in the aluminum gallium nitride layer directly under the gate electrode, or in the aluminum gallium nitride layer between the aluminum gallium nitride layer directly under the gate electrode and the aluminum gallium nitride layer directly under the drain electrode.

9. The HEMT of claim 8 , wherein the stressor is closer to the drain electrode and farther from the gate electrode.

10. The HEMT of claim 6 , further comprising a plurality of the stressors embedded in the aluminum gallium nitride layer.

11. The HEMT of claim 6 , wherein the stressor comprises a tensile stress.

12. The HEMT of claim 6 , wherein the stressor is silicon oxide or silicon nitride.

13. The HEMT of claim 6 , wherein the stressor is a silicon oxide formed by a chemical vapor deposition process.

14. The HEMT of claim 6 , wherein a thickness of the stressor is smaller than a thickness of the aluminum gallium nitride layer.

15. A method of adjusting an electron density of a two-dimensional electron gas (2DEG), comprising:
providing a gallium nitride layer and an aluminum gallium nitride layer, wherein the aluminum gallium nitride layer contacts the gallium nitride layer, a source electrode, a drain electrode and a gate electrode are disposed on the aluminum gallium nitride layer, the aluminum gallium nitride layer comprises a tensile stress, and the 2DEG is formed within the gallium nitride layer; and
performing a step selected from step A and step B, wherein:
Step A comprises forming at least one silicon oxide layer embedded in the aluminum gallium nitride layer, wherein the silicon oxide layer is formed by a flowable chemical vapor deposition, the silicon oxide layer increases the tensile stress in the aluminum gallium nitride layer and increases an electron density of the 2DEG;
Step B comprises forming at least one stressor embedded in the aluminum gallium nitride layer, wherein the stressor decreases the tensile stress in the aluminum gallium nitride layer and decreases the electron density of the 2DEG.

16. The method of adjusting an electron density of a 2DEG of claim 15 , wherein the silicon oxide layer is disposed in the aluminum gallium nitride layer directly under the source electrode, in the aluminum gallium nitride layer directly under the drain electrode, or in the aluminum gallium nitride layer between the aluminum gallium nitride layer directly under the source electrode and the aluminum gallium nitride layer directly under the drain electrode.

17. The method of adjusting an electron density of a 2DEG of claim 9 , wherein the stressor is disposed in the aluminum gallium nitride layer directly under the drain electrode, in the aluminum gallium nitride layer directly under the gate electrode, or in the aluminum gallium nitride layer between the aluminum gallium nitride layer directly under the gate electrode and the aluminum gallium nitride layer directly under the drain electrode.

18. The method of adjusting an electron density of a 2DEG of claim 15 , wherein steps of fabricating the silicon oxide layer comprise:
forming a trench in the aluminum gallium nitride layer;
performing a flowable chemical vapor deposition to form the silicon oxide layer in the trench;
curing the silicon oxide layer by a thermal process; and
planarizing the silicon oxide layer to make a top surface of the silicon oxide layer align with a top surface of the aluminum gallium nitride layer.

19. The method of adjusting an electron density of a 2DEG of claim 15 , wherein steps of fabricating the stressor comprise:
forming a trench in the aluminum gallium nitride layer;
performing a chemical vapor deposition process to form the stressor in the trench; and
planarizing the stressor to make a top surface of the stressor align with a top surface of the aluminum gallium nitride layer.

Assignees

• United Microelectronics Corp

Inventors

• Lee Kai-Lin
• Lee Zhi-Cheng
• Chen Wei-Jen

Classifications

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title

• H10P14/6334

  using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition (deposition by physical ablation of a target H10P14/6329) · CPC title

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title

• H10D62/824

  comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions · CPC title